On Thu, Jan 25, 2024 at 12:28:04PM +0200, Ville Syrjala wrote: > From: Ville Syrjälä <ville.syrj...@linux.intel.com> > > 0x108100 and 0x1080c0 have been around since snb. Rename the > defines appropriately. > > v2: Rebase > > Cc: Paz Zcharya <p...@chromium.org> > Reviewed-by: Andrzej Hajda <andrzej.ha...@intel.com> > Signed-off-by: Ville Syrjälä <ville.syrj...@linux.intel.com>
Hi Ville, Thank you so much for this incredible series. It solves the issue regarding MTL initial plane readout that Andrzej Hajda and I worked on in https://patchwork.freedesktop.org/patch/570811/?series=127130&rev=2 In addition, it solved the issue with the new GOP. I tested it on two different devices with Meteor Lake and it worked perfectly: no i915 errors, no flickers or observable issues. Tested-by: Paz Zcharya <p...@chromium.org> > --- > drivers/gpu/drm/i915/gem/i915_gem_stolen.c | 4 ++-- > drivers/gpu/drm/i915/gt/intel_ggtt.c | 2 +- > drivers/gpu/drm/i915/gt/intel_region_lmem.c | 2 +- > drivers/gpu/drm/i915/i915_reg.h | 7 ++++--- > 4 files changed, 8 insertions(+), 7 deletions(-) > > diff --git a/drivers/gpu/drm/i915/gem/i915_gem_stolen.c > b/drivers/gpu/drm/i915/gem/i915_gem_stolen.c > index 9ddcae9b3997..ad6dd7f3259b 100644 > --- a/drivers/gpu/drm/i915/gem/i915_gem_stolen.c > +++ b/drivers/gpu/drm/i915/gem/i915_gem_stolen.c > @@ -935,7 +935,7 @@ i915_gem_stolen_lmem_setup(struct drm_i915_private *i915, > u16 type, > GEM_BUG_ON((dsm_base + dsm_size) > lmem_size); > } else { > /* Use DSM base address instead for stolen memory */ > - dsm_base = intel_uncore_read64(uncore, GEN12_DSMBASE) & > GEN12_BDSM_MASK; > + dsm_base = intel_uncore_read64(uncore, GEN6_DSMBASE) & > GEN11_BDSM_MASK; > if (WARN_ON(lmem_size < dsm_base)) > return ERR_PTR(-ENODEV); > dsm_size = ALIGN_DOWN(lmem_size - dsm_base, SZ_1M); > @@ -943,7 +943,7 @@ i915_gem_stolen_lmem_setup(struct drm_i915_private *i915, > u16 type, > > if (i915_direct_stolen_access(i915)) { > drm_dbg(&i915->drm, "Using direct DSM access\n"); > - io_start = intel_uncore_read64(uncore, GEN12_DSMBASE) & > GEN12_BDSM_MASK; > + io_start = intel_uncore_read64(uncore, GEN6_DSMBASE) & > GEN11_BDSM_MASK; > io_size = dsm_size; > } else if (pci_resource_len(pdev, GEN12_LMEM_BAR) < lmem_size) { > io_start = 0; > diff --git a/drivers/gpu/drm/i915/gt/intel_ggtt.c > b/drivers/gpu/drm/i915/gt/intel_ggtt.c > index bce5d8025340..ec1cbe229f0e 100644 > --- a/drivers/gpu/drm/i915/gt/intel_ggtt.c > +++ b/drivers/gpu/drm/i915/gt/intel_ggtt.c > @@ -1163,7 +1163,7 @@ static int ggtt_probe_common(struct i915_ggtt *ggtt, > u64 size) > > if (i915_direct_stolen_access(i915)) { > drm_dbg(&i915->drm, "Using direct GSM access\n"); > - phys_addr = intel_uncore_read64(uncore, GEN12_GSMBASE) & > GEN12_BDSM_MASK; > + phys_addr = intel_uncore_read64(uncore, GEN6_GSMBASE) & > GEN11_BDSM_MASK; > } else { > phys_addr = pci_resource_start(pdev, GEN4_GTTMMADR_BAR) + > gen6_gttadr_offset(i915); > } > diff --git a/drivers/gpu/drm/i915/gt/intel_region_lmem.c > b/drivers/gpu/drm/i915/gt/intel_region_lmem.c > index af357089da6e..51bb27e10a4f 100644 > --- a/drivers/gpu/drm/i915/gt/intel_region_lmem.c > +++ b/drivers/gpu/drm/i915/gt/intel_region_lmem.c > @@ -240,7 +240,7 @@ static struct intel_memory_region *setup_lmem(struct > intel_gt *gt) > lmem_size -= tile_stolen; > } else { > /* Stolen starts from GSMBASE without CCS */ > - lmem_size = intel_uncore_read64(&i915->uncore, GEN12_GSMBASE); > + lmem_size = intel_uncore_read64(&i915->uncore, GEN6_GSMBASE); > } > > i915_resize_lmem_bar(i915, lmem_size); > diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h > index b5f5e0bc6608..1ad55aafe679 100644 > --- a/drivers/gpu/drm/i915/i915_reg.h > +++ b/drivers/gpu/drm/i915/i915_reg.h > @@ -6323,9 +6323,10 @@ enum skl_power_gate { > #define GMS_MASK REG_GENMASK(15, 8) > #define GGMS_MASK REG_GENMASK(7, 6) > > -#define GEN12_GSMBASE _MMIO(0x108100) > -#define GEN12_DSMBASE _MMIO(0x1080C0) > -#define GEN12_BDSM_MASK REG_GENMASK64(63, 20) > +#define GEN6_GSMBASE _MMIO(0x108100) > +#define GEN6_DSMBASE _MMIO(0x1080C0) > +#define GEN6_BDSM_MASK REG_GENMASK64(31, 20) > +#define GEN11_BDSM_MASK REG_GENMASK64(63, 20) > > #define XEHP_CLOCK_GATE_DIS _MMIO(0x101014) > #define SGSI_SIDECLK_DIS REG_BIT(17) > -- > 2.43.0 >
