On 1/29/2024 11:25 PM, Imre Deak wrote:
Add a workaround to fix BS (blank start) to BS jitter fixes on non-UHBR MST/FEC and UHBR links. Bspec doesn't provide an actual WA ID for this.Bspec: 65448, 50054 Signed-off-by: Imre Deak <imre.d...@intel.com> --- drivers/gpu/drm/i915/display/intel_display.c | 3 +++ drivers/gpu/drm/i915/i915_reg.h | 1 + 2 files changed, 4 insertions(+) diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c index e0b75aa18ae33..72a852cccd3f3 100644 --- a/drivers/gpu/drm/i915/display/intel_display.c +++ b/drivers/gpu/drm/i915/display/intel_display.c @@ -432,6 +432,9 @@ void intel_enable_transcoder(const struct intel_crtc_state *new_crtc_state) u32 clear = DP_DSC_INSERT_SF_AT_EOL_WA; u32 set = 0;+ if (DISPLAY_VER(dev_priv) == 14)+ set |= DP_FEC_BS_JITTER_WA; + intel_de_rmw(dev_priv, hsw_chicken_trans_reg(dev_priv, cpu_transcoder), clear, set); diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h index 9873daa16c6a1..d86e904ffe893 100644 --- a/drivers/gpu/drm/i915/i915_reg.h +++ b/drivers/gpu/drm/i915/i915_reg.h @@ -4619,6 +4619,7 @@ #define DDIE_TRAINING_OVERRIDE_ENABLE REG_BIT(17) /* CHICKEN_TRANS_A only */ #define DDIE_TRAINING_OVERRIDE_VALUE REG_BIT(16) /* CHICKEN_TRANS_A only */ #define PSR2_ADD_VERTICAL_LINE_COUNT REG_BIT(15) +#define DP_FEC_BS_JITTER_WA REG_BIT(15)
Was wondering if this is for MTL+, but it seems this is required only for MTL.
Patch LGTM. Reviewed-by: Ankit Nautiyal <ankit.k.nauti...@intel.com>
#define PSR2_VSC_ENABLE_PROG_HEADER REG_BIT(12) #define DP_DSC_INSERT_SF_AT_EOL_WA REG_BIT(4)
