On Fri, 12 Apr 2024, Ville Syrjala <ville.syrj...@linux.intel.com> wrote: > From: Ville Syrjälä <ville.syrj...@linux.intel.com> > > Add consistent definitions for the per-lane PHY TX registers > on bxt/glk. The current situation is a slight mess with some > registers having a LN0 define, while others have a parametrized > per-lane definition.
*definitions in the subject. -- Jani Nikula, Intel
