On Thu, 16 May 2024, Ville Syrjala <[email protected]> wrote: > From: Ville Syrjälä <[email protected]> > > Rename the selective fetch plane registers to match the spec. > > Signed-off-by: Ville Syrjälä <[email protected]>
Reviewed-by: Jani Nikula <[email protected]> > --- > drivers/gpu/drm/i915/display/intel_psr_regs.h | 10 +++++----- > drivers/gpu/drm/i915/display/skl_universal_plane.c | 12 ++++++------ > 2 files changed, 11 insertions(+), 11 deletions(-) > > diff --git a/drivers/gpu/drm/i915/display/intel_psr_regs.h > b/drivers/gpu/drm/i915/display/intel_psr_regs.h > index 47e3a2e2977c..f0bd0a726d7a 100644 > --- a/drivers/gpu/drm/i915/display/intel_psr_regs.h > +++ b/drivers/gpu/drm/i915/display/intel_psr_regs.h > @@ -276,23 +276,23 @@ > _SEL_FETCH_PLANE_BASE_A(plane)) > > #define _SEL_FETCH_PLANE_CTL_1_A 0x70890 > -#define PLANE_SEL_FETCH_CTL(pipe, plane) _MMIO(_SEL_FETCH_PLANE_BASE(pipe, > plane) + \ > +#define SEL_FETCH_PLANE_CTL(pipe, plane) _MMIO(_SEL_FETCH_PLANE_BASE(pipe, > plane) + \ > _SEL_FETCH_PLANE_CTL_1_A - \ > _SEL_FETCH_PLANE_BASE_1_A) > -#define PLANE_SEL_FETCH_CTL_ENABLE REG_BIT(31) > +#define SEL_FETCH_PLANE_CTL_ENABLE REG_BIT(31) > > #define _SEL_FETCH_PLANE_POS_1_A 0x70894 > -#define PLANE_SEL_FETCH_POS(pipe, plane) _MMIO(_SEL_FETCH_PLANE_BASE(pipe, > plane) + \ > +#define SEL_FETCH_PLANE_POS(pipe, plane) _MMIO(_SEL_FETCH_PLANE_BASE(pipe, > plane) + \ > _SEL_FETCH_PLANE_POS_1_A - \ > _SEL_FETCH_PLANE_BASE_1_A) > > #define _SEL_FETCH_PLANE_SIZE_1_A 0x70898 > -#define PLANE_SEL_FETCH_SIZE(pipe, plane) _MMIO(_SEL_FETCH_PLANE_BASE(pipe, > plane) + \ > +#define SEL_FETCH_PLANE_SIZE(pipe, plane) _MMIO(_SEL_FETCH_PLANE_BASE(pipe, > plane) + \ > _SEL_FETCH_PLANE_SIZE_1_A - \ > _SEL_FETCH_PLANE_BASE_1_A) > > #define _SEL_FETCH_PLANE_OFFSET_1_A 0x7089C > -#define PLANE_SEL_FETCH_OFFSET(pipe, plane) > _MMIO(_SEL_FETCH_PLANE_BASE(pipe, plane) + \ > +#define SEL_FETCH_PLANE_OFFSET(pipe, plane) > _MMIO(_SEL_FETCH_PLANE_BASE(pipe, plane) + \ > _SEL_FETCH_PLANE_OFFSET_1_A - > \ > _SEL_FETCH_PLANE_BASE_1_A) > > diff --git a/drivers/gpu/drm/i915/display/skl_universal_plane.c > b/drivers/gpu/drm/i915/display/skl_universal_plane.c > index d0bfee2ca643..6601baf18ae4 100644 > --- a/drivers/gpu/drm/i915/display/skl_universal_plane.c > +++ b/drivers/gpu/drm/i915/display/skl_universal_plane.c > @@ -705,7 +705,7 @@ static void icl_plane_disable_sel_fetch_arm(struct > intel_plane *plane, > if (!crtc_state->enable_psr2_sel_fetch) > return; > > - intel_de_write_fw(i915, PLANE_SEL_FETCH_CTL(pipe, plane->id), 0); > + intel_de_write_fw(i915, SEL_FETCH_PLANE_CTL(pipe, plane->id), 0); > } > > static void > @@ -1304,7 +1304,7 @@ static void icl_plane_update_sel_fetch_noarm(struct > intel_plane *plane, > > val = (clip->y1 + plane_state->uapi.dst.y1) << 16; > val |= plane_state->uapi.dst.x1; > - intel_de_write_fw(i915, PLANE_SEL_FETCH_POS(pipe, plane->id), val); > + intel_de_write_fw(i915, SEL_FETCH_PLANE_POS(pipe, plane->id), val); > > x = plane_state->view.color_plane[color_plane].x; > > @@ -1319,13 +1319,13 @@ static void icl_plane_update_sel_fetch_noarm(struct > intel_plane *plane, > > val = y << 16 | x; > > - intel_de_write_fw(i915, PLANE_SEL_FETCH_OFFSET(pipe, plane->id), > + intel_de_write_fw(i915, SEL_FETCH_PLANE_OFFSET(pipe, plane->id), > val); > > /* Sizes are 0 based */ > val = (drm_rect_height(clip) - 1) << 16; > val |= (drm_rect_width(&plane_state->uapi.src) >> 16) - 1; > - intel_de_write_fw(i915, PLANE_SEL_FETCH_SIZE(pipe, plane->id), val); > + intel_de_write_fw(i915, SEL_FETCH_PLANE_SIZE(pipe, plane->id), val); > } > > static void > @@ -1414,8 +1414,8 @@ static void icl_plane_update_sel_fetch_arm(struct > intel_plane *plane, > return; > > if (drm_rect_height(&plane_state->psr2_sel_fetch_area) > 0) > - intel_de_write_fw(i915, PLANE_SEL_FETCH_CTL(pipe, plane->id), > - PLANE_SEL_FETCH_CTL_ENABLE); > + intel_de_write_fw(i915, SEL_FETCH_PLANE_CTL(pipe, plane->id), > + SEL_FETCH_PLANE_CTL_ENABLE); > else > icl_plane_disable_sel_fetch_arm(plane, crtc_state); > } -- Jani Nikula, Intel
