Aux RD Interval value depends on the value read from the dpcd register which is updated from the sink device use flseep thereby we adhere to the Documentation/timers/timers-howto.rst
Signed-off-by: Srikanth V NagaVenkata <[email protected]> Signed-off-by: Arun R Murthy <[email protected]> --- drivers/gpu/drm/i915/display/intel_dp_link_training.c | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/drivers/gpu/drm/i915/display/intel_dp_link_training.c b/drivers/gpu/drm/i915/display/intel_dp_link_training.c index 397cc4ebae52..f41b69840ad9 100644 --- a/drivers/gpu/drm/i915/display/intel_dp_link_training.c +++ b/drivers/gpu/drm/i915/display/intel_dp_link_training.c @@ -898,7 +898,7 @@ intel_dp_link_training_clock_recovery(struct intel_dp *intel_dp, voltage_tries = 1; for (cr_tries = 0; cr_tries < max_cr_tries; ++cr_tries) { - usleep_range(delay_us, 2 * delay_us); + fsleep(delay_us); if (drm_dp_dpcd_read_phy_link_status(&intel_dp->aux, dp_phy, link_status) < 0) { @@ -1040,7 +1040,7 @@ intel_dp_link_training_channel_equalization(struct intel_dp *intel_dp, } for (tries = 0; tries < 5; tries++) { - usleep_range(delay_us, 2 * delay_us); + fsleep(delay_us); if (drm_dp_dpcd_read_phy_link_status(&intel_dp->aux, dp_phy, link_status) < 0) { @@ -1417,7 +1417,7 @@ intel_dp_128b132b_lane_eq(struct intel_dp *intel_dp, deadline = jiffies + msecs_to_jiffies_timeout(400); for (try = 0; try < max_tries; try++) { - usleep_range(delay_us, 2 * delay_us); + fsleep(delay_us); /* * The delay may get updated. The transmitter shall read the -- 2.25.1
