From: Ville Syrjälä <[email protected]>

Add a proper bitmask definition for the pre-bdw fault
virtual address bits insted of abusing PAGE_MASK.

Signed-off-by: Ville Syrjälä <[email protected]>
---
 drivers/gpu/drm/i915/gt/intel_gt.c      | 8 +++++---
 drivers/gpu/drm/i915/gt/intel_gt_regs.h | 1 +
 2 files changed, 6 insertions(+), 3 deletions(-)

diff --git a/drivers/gpu/drm/i915/gt/intel_gt.c 
b/drivers/gpu/drm/i915/gt/intel_gt.c
index 04b43852a397..b8189754edb7 100644
--- a/drivers/gpu/drm/i915/gt/intel_gt.c
+++ b/drivers/gpu/drm/i915/gt/intel_gt.c
@@ -302,17 +302,19 @@ static void gen6_check_faults(struct intel_gt *gt)
 {
        struct intel_engine_cs *engine;
        enum intel_engine_id id;
-       unsigned long fault;
 
        for_each_engine(engine, gt, id) {
+               u32 fault;
+
                fault = GEN6_RING_FAULT_REG_READ(engine);
+
                if (fault & RING_FAULT_VALID) {
                        gt_dbg(gt, "Unexpected fault\n"
-                              "\tAddr: 0x%08lx\n"
+                              "\tAddr: 0x%08x\n"
                               "\tAddress space: %s\n"
                               "\tSource ID: %d\n"
                               "\tType: %d\n",
-                              fault & PAGE_MASK,
+                              fault & RING_FAULT_VADDR_MASK,
                               fault & RING_FAULT_GTTSEL_MASK ?
                               "GGTT" : "PPGTT",
                               REG_FIELD_GET(RING_FAULT_SRCID_MASK, fault),
diff --git a/drivers/gpu/drm/i915/gt/intel_gt_regs.h 
b/drivers/gpu/drm/i915/gt/intel_gt_regs.h
index 1d318993a652..c58192e6f078 100644
--- a/drivers/gpu/drm/i915/gt/intel_gt_regs.h
+++ b/drivers/gpu/drm/i915/gt/intel_gt_regs.h
@@ -326,6 +326,7 @@
                                                            
_RING_FAULT_REG_VCS, \
                                                            
_RING_FAULT_REG_VECS, \
                                                            
_RING_FAULT_REG_BCS))
+#define   RING_FAULT_VADDR_MASK                        REG_GENMASK(31, 12) /* 
pre-bdw */
 #define   RING_FAULT_ENGINE_ID_MASK            REG_GENMASK(16, 12) /* bdw+ */
 #define   RING_FAULT_GTTSEL_MASK               REG_BIT(11) /* pre-bdw */
 #define   RING_FAULT_SRCID_MASK                        REG_GENMASK(10, 3)
-- 
2.45.3

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