Introduce helpers to get and set TRANS_VTOTAL registers.
This will pave way to avoid reading/writing VTOTAL.Vtotal bits for
platforms that always use VRR timing generator.
Signed-off-by: Ankit Nautiyal <ankit.k.nauti...@intel.com>
---
drivers/gpu/drm/i915/display/intel_display.c | 41 +++++++++++++-------
1 file changed, 27 insertions(+), 14 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_display.c
b/drivers/gpu/drm/i915/display/intel_display.c
index ae1dc32044fb..fa9c6793357e 100644
--- a/drivers/gpu/drm/i915/display/intel_display.c
+++ b/drivers/gpu/drm/i915/display/intel_display.c
@@ -2638,6 +2638,15 @@ void intel_cpu_transcoder_set_m2_n2(struct intel_crtc
*crtc,
PIPE_LINK_N2(display, transcoder));
}
+static void intel_crtc_set_vtotal(struct intel_display *display,
+ enum transcoder cpu_transcoder,
+ u32 crtc_vdisplay, u32 crtc_vtotal)
+{
+ intel_de_write(display, TRANS_VTOTAL(display, cpu_transcoder),
+ VACTIVE(crtc_vdisplay - 1) |
+ VTOTAL(crtc_vtotal - 1));
+}
+
static void intel_set_transcoder_timings(const struct intel_crtc_state
*crtc_state)
{
struct intel_display *display = to_intel_display(crtc_state);
@@ -2702,9 +2711,8 @@ static void intel_set_transcoder_timings(const struct
intel_crtc_state *crtc_sta
HSYNC_START(adjusted_mode->crtc_hsync_start - 1) |
HSYNC_END(adjusted_mode->crtc_hsync_end - 1));
- intel_de_write(display, TRANS_VTOTAL(display, cpu_transcoder),
- VACTIVE(crtc_vdisplay - 1) |
- VTOTAL(crtc_vtotal - 1));
+ intel_crtc_set_vtotal(display, cpu_transcoder, crtc_vdisplay,
crtc_vtotal);
+
intel_de_write(display, TRANS_VBLANK(display, cpu_transcoder),
VBLANK_START(crtc_vblank_start - 1) |
VBLANK_END(crtc_vblank_end - 1));
@@ -2718,9 +2726,8 @@ static void intel_set_transcoder_timings(const struct
intel_crtc_state *crtc_sta
* bits. */
if (display->platform.haswell && cpu_transcoder == TRANSCODER_EDP &&
(pipe == PIPE_B || pipe == PIPE_C))
- intel_de_write(display, TRANS_VTOTAL(display, pipe),
- VACTIVE(crtc_vdisplay - 1) |
- VTOTAL(crtc_vtotal - 1));
+ intel_crtc_set_vtotal(display, (enum transcoder)pipe,
+ crtc_vdisplay, crtc_vtotal);
}
static void intel_set_transcoder_timings_lrr(const struct intel_crtc_state
*crtc_state)
@@ -2766,9 +2773,7 @@ static void intel_set_transcoder_timings_lrr(const struct
intel_crtc_state *crtc
* The double buffer latch point for TRANS_VTOTAL
* is the transcoder's undelayed vblank.
*/
- intel_de_write(display, TRANS_VTOTAL(display, cpu_transcoder),
- VACTIVE(crtc_vdisplay - 1) |
- VTOTAL(crtc_vtotal - 1));
+ intel_crtc_set_vtotal(display, cpu_transcoder, crtc_vdisplay,
crtc_vtotal);
intel_vrr_set_fixed_rr_timings(crtc_state);
intel_vrr_transcoder_enable(crtc_state);
@@ -2806,6 +2811,17 @@ static bool intel_pipe_is_interlaced(const struct
intel_crtc_state *crtc_state)
TRANSCONF(display, cpu_transcoder)) &
TRANSCONF_INTERLACE_MASK;
}
+static void intel_crtc_get_vtotal(struct intel_crtc_state *crtc_state)
+{
+ struct intel_display *display = to_intel_display(crtc_state);
+ enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;
+ struct drm_display_mode *adjusted_mode = &crtc_state->hw.adjusted_mode;
+ u32 tmp = intel_de_read(display, TRANS_VTOTAL(display, cpu_transcoder));
+
+ adjusted_mode->crtc_vdisplay = REG_FIELD_GET(VACTIVE_MASK, tmp) + 1;
+ adjusted_mode->crtc_vtotal = REG_FIELD_GET(VTOTAL_MASK, tmp) + 1;
+}
+
static void intel_get_transcoder_timings(struct intel_crtc *crtc,
struct intel_crtc_state *pipe_config)
{
@@ -2829,9 +2845,7 @@ static void intel_get_transcoder_timings(struct
intel_crtc *crtc,
adjusted_mode->crtc_hsync_start = REG_FIELD_GET(HSYNC_START_MASK, tmp)
+ 1;
adjusted_mode->crtc_hsync_end = REG_FIELD_GET(HSYNC_END_MASK, tmp) + 1;
- tmp = intel_de_read(display, TRANS_VTOTAL(display, cpu_transcoder));
- adjusted_mode->crtc_vdisplay = REG_FIELD_GET(VACTIVE_MASK, tmp) + 1;
- adjusted_mode->crtc_vtotal = REG_FIELD_GET(VTOTAL_MASK, tmp) + 1;
+ intel_crtc_get_vtotal(pipe_config);
/* FIXME TGL+ DSI transcoders have this! */
if (!transcoder_is_dsi(cpu_transcoder)) {
@@ -8168,8 +8182,7 @@ void i830_enable_pipe(struct intel_display *display, enum
pipe pipe)
HBLANK_START(640 - 1) | HBLANK_END(800 - 1));
intel_de_write(display, TRANS_HSYNC(display, cpu_transcoder),
HSYNC_START(656 - 1) | HSYNC_END(752 - 1));
- intel_de_write(display, TRANS_VTOTAL(display, cpu_transcoder),
- VACTIVE(480 - 1) | VTOTAL(525 - 1));
+ intel_crtc_set_vtotal(display, cpu_transcoder, 480, 525);
intel_de_write(display, TRANS_VBLANK(display, cpu_transcoder),
VBLANK_START(480 - 1) | VBLANK_END(525 - 1));
intel_de_write(display, TRANS_VSYNC(display, cpu_transcoder),
--
2.45.2
