On Tue, Mar 25, 2025 at 11:52:24AM +0530, Nautiyal, Ankit K wrote:
>
> On 3/24/2025 11:32 PM, Ville Syrjälä wrote:
> > On Mon, Mar 24, 2025 at 07:02:47PM +0530, Ankit Nautiyal wrote:
> >> Introduce helpers to get and set TRANS_VTOTAL registers.
> >> This will pave way to avoid reading/writing VTOTAL.Vtotal bits for
> >> platforms that always use VRR timing generator.
> >>
> >> Signed-off-by: Ankit Nautiyal <ankit.k.nauti...@intel.com>
> >> ---
> >> drivers/gpu/drm/i915/display/intel_display.c | 41 +++++++++++++-------
> >> 1 file changed, 27 insertions(+), 14 deletions(-)
> >>
> >> diff --git a/drivers/gpu/drm/i915/display/intel_display.c
> >> b/drivers/gpu/drm/i915/display/intel_display.c
> >> index ae1dc32044fb..fa9c6793357e 100644
> >> --- a/drivers/gpu/drm/i915/display/intel_display.c
> >> +++ b/drivers/gpu/drm/i915/display/intel_display.c
> >> @@ -2638,6 +2638,15 @@ void intel_cpu_transcoder_set_m2_n2(struct
> >> intel_crtc *crtc,
> >> PIPE_LINK_N2(display, transcoder));
> >> }
> >>
> >> +static void intel_crtc_set_vtotal(struct intel_display *display,
> >> + enum transcoder cpu_transcoder,
> >> + u32 crtc_vdisplay, u32 crtc_vtotal)
> >> +{
> >> + intel_de_write(display, TRANS_VTOTAL(display, cpu_transcoder),
> >> + VACTIVE(crtc_vdisplay - 1) |
> >> + VTOTAL(crtc_vtotal - 1));
> >> +}
> >> +
> >> static void intel_set_transcoder_timings(const struct intel_crtc_state
> >> *crtc_state)
> >> {
> >> struct intel_display *display = to_intel_display(crtc_state);
> >> @@ -2702,9 +2711,8 @@ static void intel_set_transcoder_timings(const
> >> struct intel_crtc_state *crtc_sta
> >> HSYNC_START(adjusted_mode->crtc_hsync_start - 1) |
> >> HSYNC_END(adjusted_mode->crtc_hsync_end - 1));
> >>
> >> - intel_de_write(display, TRANS_VTOTAL(display, cpu_transcoder),
> >> - VACTIVE(crtc_vdisplay - 1) |
> >> - VTOTAL(crtc_vtotal - 1));
> >> + intel_crtc_set_vtotal(display, cpu_transcoder, crtc_vdisplay,
> >> crtc_vtotal);
> >> +
> >> intel_de_write(display, TRANS_VBLANK(display, cpu_transcoder),
> >> VBLANK_START(crtc_vblank_start - 1) |
> >> VBLANK_END(crtc_vblank_end - 1));
> >> @@ -2718,9 +2726,8 @@ static void intel_set_transcoder_timings(const
> >> struct intel_crtc_state *crtc_sta
> >> * bits. */
> >> if (display->platform.haswell && cpu_transcoder == TRANSCODER_EDP &&
> >> (pipe == PIPE_B || pipe == PIPE_C))
> >> - intel_de_write(display, TRANS_VTOTAL(display, pipe),
> >> - VACTIVE(crtc_vdisplay - 1) |
> >> - VTOTAL(crtc_vtotal - 1));
> >> + intel_crtc_set_vtotal(display, (enum transcoder)pipe,
> >> + crtc_vdisplay, crtc_vtotal);
> >> }
> >>
> >> static void intel_set_transcoder_timings_lrr(const struct
> >> intel_crtc_state *crtc_state)
> >> @@ -2766,9 +2773,7 @@ static void intel_set_transcoder_timings_lrr(const
> >> struct intel_crtc_state *crtc
> >> * The double buffer latch point for TRANS_VTOTAL
> >> * is the transcoder's undelayed vblank.
> >> */
> >> - intel_de_write(display, TRANS_VTOTAL(display, cpu_transcoder),
> >> - VACTIVE(crtc_vdisplay - 1) |
> >> - VTOTAL(crtc_vtotal - 1));
> >> + intel_crtc_set_vtotal(display, cpu_transcoder, crtc_vdisplay,
> >> crtc_vtotal);
> > Not really a fan of special casing this that much. I think we should
> > probably handle it the same way we deal with the VBLANK_START vs.
> > TRANS_SET_CONTEXT_LATENCY.
> Hmm I can do away with the helper, and avoid having VTOTAL.Vtotal bits
> set for specific cases in intel_vrr_set_transcoder_{timings, timings_lrr}.
> >
> > The readount should perhaps just be handled in intel_vrr_get_config().
>
> I can try this out.
>
>
> > But I think we'll need somehting like transcoder_has_vrr() to exclude
> > the DSI transcoders in a consistent way.
>
> If I understand correctly you mean that wherever we are avoiding VRR
> related register read/write for DSI, use trans_has_vrr() instead of
> !transcoder_is_dsi(),
>
> with trans_has_vrr having call to transcoder_is_dsi()?
Yeah something like that.
>
> Will perhaps add this as a separate patch.
These two last patches aren't needed to get this stuff actually
working right? Or is the GOP leaving TRANS_VOTAL.vtotal unset?
So yeah, if not needed right now probably best to leave this
stuff for a seaprate series.
--
Ville Syrjälä
Intel
