DG2 does not actually support UHBR 13.5 link rate. Reduce DG2 max
link rate to UHBR 10, and drop UHBR 13.5 from the supported
source rates for DG2.
The VBT on DG2 platforms should already limit the max link rate to
UHBR 10, but be defensive about it
v2: Reframed the commit msg (Jani)
v4: Reframed the commit msg & update the max rate supported (Jani)
v5: Reframed the commit msg (Jani)
v6: Reframed the commit msg (Jani)
Signed-off-by: Arun R Murthy <arun.r.mur...@intel.com>
---
drivers/gpu/drm/i915/display/intel_dp.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_dp.c
b/drivers/gpu/drm/i915/display/intel_dp.c
index
f21f9b441fc2a4e644c69410e6ec6b3d37907478..92bca701a989b03e2ad4b3d9e7d0a9ef12567e5a
100644
--- a/drivers/gpu/drm/i915/display/intel_dp.c
+++ b/drivers/gpu/drm/i915/display/intel_dp.c
@@ -481,7 +481,7 @@ bool intel_dp_has_joiner(struct intel_dp *intel_dp)
static int dg2_max_source_rate(struct intel_dp *intel_dp)
{
- return intel_dp_is_edp(intel_dp) ? 810000 : 1350000;
+ return intel_dp_is_edp(intel_dp) ? 810000 : 1000000;
}
static int icl_max_source_rate(struct intel_dp *intel_dp)
@@ -550,7 +550,7 @@ intel_dp_set_source_rates(struct intel_dp *intel_dp)
};
static const int icl_rates[] = {
162000, 216000, 270000, 324000, 432000, 540000, 648000, 810000,
- 1000000, 1350000,
+ 1000000,
};
static const int bxt_rates[] = {
162000, 216000, 243000, 270000, 324000, 432000, 540000
--
2.25.1
