Re: [PATCH v2 02/13] drm/i915/vrr: Add functions to read out vmin/vmax stuff

Wed, 23 Apr 2025 06:39:23 -0700 


On 4/23/2025 6:47 PM, Nautiyal, Ankit K wrote:


On 4/21/2025 9:18 PM, Mitul Golani wrote:

From: Ville Syrjälä <ville.syrj...@linux.intel.com>

Calculate delayed vblank start position with the help of added
vmin/vmax stuff for next frame and final computation.

Signed-off-by: Ville Syrjälä <ville.syrj...@linux.intel.com>
Signed-off-by: Mitul Golani <mitulkumar.ajitkumar.gol...@intel.com>
---
  drivers/gpu/drm/i915/display/intel_vrr.c      | 57 +++++++++++++++++++
  drivers/gpu/drm/i915/display/intel_vrr.h      |  5 ++
  drivers/gpu/drm/i915/display/intel_vrr_regs.h | 44 ++++++++++++++
  3 files changed, 106 insertions(+)


diff --git a/drivers/gpu/drm/i915/display/intel_vrr.c 
b/drivers/gpu/drm/i915/display/intel_vrr.c

index adfd231eb578..1c0eaa08927b 100644
--- a/drivers/gpu/drm/i915/display/intel_vrr.c
+++ b/drivers/gpu/drm/i915/display/intel_vrr.c

@@ -746,3 +746,60 @@ void intel_vrr_get_config(struct 
intel_crtc_state *crtc_state)

      if (crtc_state->vrr.enable)
          crtc_state->mode_flags |= I915_MODE_FLAG_VRR;
  }
+

+int intel_vrr_dcb_vmin_vblank_start_next(const struct 
intel_crtc_state *crtc_state)

+{
+    struct intel_display *display = to_intel_display(crtc_state);
+    enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;
+    u32 tmp;
+
+    tmp = intel_de_read(display,

+                TRANS_VRR_DCB_ADJ_FLIPLINE_CFG(display, 
cpu_transcoder));



These might be needing a check for HAS_DC_BALANCE. This might explain 
the BAT issues.




Scratch that, these are used only when vrr.dc_balance.enable is set, so 
these might not be the cause.





Regards,

Ankit


+
+    if (REG_FIELD_GET(VRR_DCB_ADJ_FLIPLINE_CNT_MASK, tmp) == 0)
+        return -1;
+
+    return intel_vrr_vblank_start(crtc_state,

+                      REG_FIELD_GET(VRR_DCB_ADJ_FLIPLINE_MASK, tmp) 
+ 1);

+}
+

+int intel_vrr_dcb_vmax_vblank_start_next(const struct 
intel_crtc_state *crtc_state)

+{
+    struct intel_display *display = to_intel_display(crtc_state);
+    enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;
+    u32 tmp;
+
+    tmp = intel_de_read(display,
+                TRANS_VRR_DCB_ADJ_VMAX_CFG(display, cpu_transcoder));
+
+    if (REG_FIELD_GET(VRR_DCB_ADJ_VMAX_CNT_MASK, tmp) == 0)
+        return -1;
+
+    return intel_vrr_vblank_start(crtc_state,
+                      REG_FIELD_GET(VRR_DCB_ADJ_VMAX_MASK, tmp) + 1);
+}
+

+int intel_vrr_dcb_vmin_vblank_start_final(const struct 
intel_crtc_state *crtc_state)

+{
+    struct intel_display *display = to_intel_display(crtc_state);
+    enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;
+    u32 tmp;
+
+    tmp = intel_de_read(display,
+                TRANS_VRR_FLIPLINE_DCB(display, cpu_transcoder));
+
+    return intel_vrr_vblank_start(crtc_state,
+                      REG_FIELD_GET(VRR_FLIPLINE_DCB_MASK, tmp) + 1);
+}
+

+int intel_vrr_dcb_vmax_vblank_start_final(const struct 
intel_crtc_state *crtc_state)

+{
+    struct intel_display *display = to_intel_display(crtc_state);
+    enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;
+    u32 tmp;
+

+    tmp = intel_de_read(display, TRANS_VRR_VMAX_DCB(display, 
cpu_transcoder));

+
+    return intel_vrr_vblank_start(crtc_state,
+                      REG_FIELD_GET(VRR_VMAX_DCB_MASK, tmp) + 1);
+}

diff --git a/drivers/gpu/drm/i915/display/intel_vrr.h 
b/drivers/gpu/drm/i915/display/intel_vrr.h

index 38bf9996b883..e62b8b50aec6 100644
--- a/drivers/gpu/drm/i915/display/intel_vrr.h
+++ b/drivers/gpu/drm/i915/display/intel_vrr.h

@@ -42,4 +42,9 @@ void intel_vrr_transcoder_disable(const struct 
intel_crtc_state *crtc_state);
  void intel_vrr_set_fixed_rr_timings(const struct intel_crtc_state 
*crtc_state);

  bool intel_vrr_always_use_vrr_tg(struct intel_display *display);

  +int intel_vrr_dcb_vmin_vblank_start_next(const struct 
intel_crtc_state *crtc_state);
+int intel_vrr_dcb_vmax_vblank_start_next(const struct 
intel_crtc_state *crtc_state);
+int intel_vrr_dcb_vmin_vblank_start_final(const struct 
intel_crtc_state *crtc_state);
+int intel_vrr_dcb_vmax_vblank_start_final(const struct 
intel_crtc_state *crtc_state);

+
  #endif /* __INTEL_VRR_H__ */

diff --git a/drivers/gpu/drm/i915/display/intel_vrr_regs.h 
b/drivers/gpu/drm/i915/display/intel_vrr_regs.h

index 6ed0e0dc97e7..2214c10d4084 100644
--- a/drivers/gpu/drm/i915/display/intel_vrr_regs.h
+++ b/drivers/gpu/drm/i915/display/intel_vrr_regs.h
@@ -9,6 +9,50 @@
  #include "intel_display_reg_defs.h"
    /* VRR registers */
+#define _TRANS_VRR_DCB_ADJ_FLIPLINE_CFG_A        0x604D4
+#define _TRANS_VRR_DCB_ADJ_FLIPLINE_CFG_B        0x614D4
+#define _TRANS_VRR_DCB_ADJ_FLIPLINE_CFG_C        0x624D4
+#define _TRANS_VRR_DCB_ADJ_FLIPLINE_CFG_D        0x634D4
+#define _TRANS_VRR_DCB_ADJ_FLIPLINE_CFG_E        0x6B4D4
+#define TRANS_VRR_DCB_ADJ_FLIPLINE_CFG(dev_priv, trans)    \
+                    _MMIO_TRANS2(dev_priv, \
+                             trans, \
+                             _TRANS_VRR_DCB_ADJ_FLIPLINE_CFG_A)
+
+#define _TRANS_VRR_DCB_ADJ_VMAX_CFG_A            0x604D8
+#define _TRANS_VRR_DCB_ADJ_VMAX_CFG_B            0x614D8
+#define _TRANS_VRR_DCB_ADJ_VMAX_CFG_C            0x624D8
+#define _TRANS_VRR_DCB_ADJ_VMAX_CFG_D            0x634D8
+#define _TRANS_VRR_DCB_ADJ_VMAX_CFG_E            0x6B4D8

+#define TRANS_VRR_DCB_ADJ_VMAX_CFG(dev_priv, trans) 
_MMIO_TRANS2(dev_priv, \

+                                     trans, \
+ _TRANS_VRR_DCB_ADJ_VMAX_CFG_A)
+
+#define _TRANS_VRR_FLIPLINE_DCB_A        0x60418
+#define _TRANS_VRR_FLIPLINE_DCB_B        0x61418
+#define _TRANS_VRR_FLIPLINE_DCB_C        0x62418
+#define _TRANS_VRR_FLIPLINE_DCB_D        0x63418
+#define _TRANS_VRR_FLIPLINE_DCB_E        0x6B418

+#define TRANS_VRR_FLIPLINE_DCB(dev_priv, trans) 
_MMIO_TRANS2(dev_priv, \

+                                 trans, \
+                                 _TRANS_VRR_FLIPLINE_DCB_A)
+
+#define _TRANS_VRR_VMAX_DCB_A            0x60414
+#define _TRANS_VRR_VMAX_DCB_B            0x61414
+#define _TRANS_VRR_VMAX_DCB_C            0x62414
+#define _TRANS_VRR_VMAX_DCB_D            0x63414
+#define _TRANS_VRR_VMAX_DCB_E            0x6B414
+#define TRANS_VRR_VMAX_DCB(dev_priv, trans) _MMIO_TRANS2(dev_priv, \
+                                 trans, \
+                                 _TRANS_VRR_VMAX_DCB_A)
+
+#define VRR_DCB_ADJ_FLIPLINE_CNT_MASK        REG_GENMASK(31, 24)
+#define VRR_DCB_ADJ_FLIPLINE_MASK        REG_GENMASK(19, 0)
+#define VRR_DCB_ADJ_VMAX_CNT_MASK        REG_GENMASK(31, 24)
+#define VRR_DCB_ADJ_VMAX_MASK            REG_GENMASK(19, 0)
+#define VRR_FLIPLINE_DCB_MASK            REG_GENMASK(19, 0)
+#define VRR_VMAX_DCB_MASK            REG_GENMASK(19, 0)
+
  #define _TRANS_VRR_CTL_A            0x60420
  #define _TRANS_VRR_CTL_B            0x61420
  #define _TRANS_VRR_CTL_C            0x62420






















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