From: Ville Syrjälä <ville.syrj...@linux.intel.com>
Pause the DMC DC balancing for the remainder of the
commit so that vmin/vmax won't change after we've baked
them into the DSB vblank evasion commands.
--v2:
- Remove typo of readding sending PUSH. (Ankit)
- Separate vrr enable structuring from Pause DSB patch. (Ankit)
Signed-off-by: Ville Syrjälä <ville.syrj...@linux.intel.com>
Signed-off-by: Mitul Golani <mitulkumar.ajitkumar.gol...@intel.com>
---
drivers/gpu/drm/i915/display/intel_display.c | 13 +++++++++++++
drivers/gpu/drm/i915/display/intel_vrr.c | 5 +++++
2 files changed, 18 insertions(+)
diff --git a/drivers/gpu/drm/i915/display/intel_display.c
b/drivers/gpu/drm/i915/display/intel_display.c
index 1cd9c65da576..e6d7a0a145d2 100644
--- a/drivers/gpu/drm/i915/display/intel_display.c
+++ b/drivers/gpu/drm/i915/display/intel_display.c
@@ -7206,6 +7206,17 @@ static void intel_atomic_dsb_finish(struct
intel_atomic_state *state,
}
if (new_crtc_state->use_dsb) {
+ /*
+ * Pause the DMC DC balancing for the remainder of the
+ * commit so that vmin/vmax won't change after we've baked
+ * them into the DSB vblank evasion commands.
+ *
+ * FIXME maybe need a small delay here to make sure DMC has
+ * finished updating the values? Or we need a better
DMC<->driver
+ * protocol that gives is real guarantees about that...
+ */
+ intel_pipedmc_dcb_disable(NULL, crtc);
+
if (intel_crtc_needs_color_update(new_crtc_state))
intel_color_commit_noarm(new_crtc_state->dsb_commit,
new_crtc_state);
@@ -7242,6 +7253,8 @@ static void intel_atomic_dsb_finish(struct
intel_atomic_state *state,
intel_vrr_send_push(new_crtc_state->dsb_commit,
new_crtc_state);
intel_dsb_wait_vblank_delay(state,
new_crtc_state->dsb_commit);
intel_vrr_check_push_sent(new_crtc_state->dsb_commit,
new_crtc_state);
+ if (new_crtc_state->vrr.dc_balance.enable)
+
intel_pipedmc_dcb_enable(new_crtc_state->dsb_commit, crtc);
intel_dsb_interrupt(new_crtc_state->dsb_commit);
}
}
diff --git a/drivers/gpu/drm/i915/display/intel_vrr.c
b/drivers/gpu/drm/i915/display/intel_vrr.c
index 86b858222b6e..0f0e21cb05a9 100644
--- a/drivers/gpu/drm/i915/display/intel_vrr.c
+++ b/drivers/gpu/drm/i915/display/intel_vrr.c
@@ -9,6 +9,7 @@
#include "i915_reg.h"
#include "intel_de.h"
#include "intel_display_types.h"
+#include "intel_dmc.h"
#include "intel_dp.h"
#include "intel_dmc_regs.h"
#include "intel_vrr.h"
@@ -602,6 +603,7 @@ bool intel_vrr_always_use_vrr_tg(struct intel_display
*display)
void intel_vrr_enable(const struct intel_crtc_state *crtc_state)
{
struct intel_display *display = to_intel_display(crtc_state);
+ struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;
u32 ctl;
@@ -639,12 +641,14 @@ void intel_vrr_enable(const struct intel_crtc_state
*crtc_state)
crtc_state->vrr.dc_balance.slope);
intel_de_write(display, PIPEDMC_DCB_VBLANK(display,
cpu_transcoder),
crtc_state->vrr.dc_balance.vblank_target);
+ intel_pipedmc_dcb_enable(NULL, crtc);
}
}
void intel_vrr_disable(const struct intel_crtc_state *old_crtc_state)
{
struct intel_display *display = to_intel_display(old_crtc_state);
+ struct intel_crtc *crtc = to_intel_crtc(old_crtc_state->uapi.crtc);
enum transcoder cpu_transcoder = old_crtc_state->cpu_transcoder;
u32 ctl;
@@ -652,6 +656,7 @@ void intel_vrr_disable(const struct intel_crtc_state
*old_crtc_state)
return;
if (HAS_VRR_DC_BALANCE(display) &&
old_crtc_state->vrr.dc_balance.enable) {
+ intel_pipedmc_dcb_disable(NULL, crtc);
intel_de_write(display, TRANS_ADAPTIVE_SYNC_DCB_CTL(display,
cpu_transcoder), 0);
intel_de_write(display, PIPEDMC_DCB_VMIN(display,
cpu_transcoder), 0);
intel_de_write(display, PIPEDMC_DCB_VMAX(display,
cpu_transcoder), 0);
--
2.48.1
