[PATCH v3 15/15] drm/i915/vrr: enable dc balance bit

[Mitul Golani]

Enable dc balance from vrr compute config and enable
double buffer adjustment bit when vrr is enabled in
adaptive vtotal mode. Along with this enable frame
counters for DC balance odd and even frame count
calculation.

--v2: Update commit message

Signed-off-by: Mitul Golani <mitulkumar.ajitkumar.gol...@intel.com>
Reviewed-by: Ankit Nautiyal <ankit.k.nauti...@intel.com>
---
 drivers/gpu/drm/i915/display/intel_vrr.c | 10 ++++++++++
 1 file changed, 10 insertions(+)

diff --git a/drivers/gpu/drm/i915/display/intel_vrr.c 
b/drivers/gpu/drm/i915/display/intel_vrr.c
index 0f0e21cb05a9..2111503dff92 100644
--- a/drivers/gpu/drm/i915/display/intel_vrr.c
+++ b/drivers/gpu/drm/i915/display/intel_vrr.c
@@ -259,7 +259,12 @@ void intel_vrr_compute_cmrr_timings(struct 
intel_crtc_state *crtc_state)
 static
 void intel_vrr_compute_vrr_timings(struct intel_crtc_state *crtc_state)
 {
+       struct intel_display *display = to_intel_display(crtc_state);
        crtc_state->vrr.enable = true;
+
+       if (HAS_VRR_DC_BALANCE(display))
+               crtc_state->vrr.dc_balance.enable = true;
+
        crtc_state->mode_flags |= I915_MODE_FLAG_VRR;
 }
 
@@ -623,6 +628,8 @@ void intel_vrr_enable(const struct intel_crtc_state 
*crtc_state)
        ctl = VRR_CTL_VRR_ENABLE | trans_vrr_ctl(crtc_state);
        if (crtc_state->cmrr.enable)
                ctl |= VRR_CTL_CMRR_ENABLE;
+       if (crtc_state->vrr.dc_balance.enable)
+               ctl |= VRR_CTL_DCB_ADJ_ENABLE;
 
        intel_de_write(display, TRANS_VRR_CTL(display, cpu_transcoder), ctl);
 
@@ -641,6 +648,9 @@ void intel_vrr_enable(const struct intel_crtc_state 
*crtc_state)
                               crtc_state->vrr.dc_balance.slope);
                intel_de_write(display, PIPEDMC_DCB_VBLANK(display, 
cpu_transcoder),
                               crtc_state->vrr.dc_balance.vblank_target);
+               /* FIXME reset counters? */
+               intel_de_write(display, TRANS_ADAPTIVE_SYNC_DCB_CTL(display, 
cpu_transcoder),
+                              ADAPTIVE_SYNC_COUNTER_EN);
                intel_pipedmc_dcb_enable(NULL, crtc);
        }
 }
-- 
2.48.1