[PATCH v4 17/17] drm/i915/vrr: Enable DC Balance bit

[Mitul Golani]

Enable DC Balance from vrr compute config and also add
enable/disable frame counters for DC Balance odd and even
frame count calculation.

--v2:
Update commit message

--v3:
- Driver should not control adjustment enable bit, as that
is already being controlled by firmware. Release bit from
driver computation.
- Commit message update.

Signed-off-by: Mitul Golani <mitulkumar.ajitkumar.gol...@intel.com>
Reviewed-by: Ankit Nautiyal <ankit.k.nauti...@intel.com>
---
 drivers/gpu/drm/i915/display/intel_vrr.c | 12 ++++++++++--
 1 file changed, 10 insertions(+), 2 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_vrr.c 
b/drivers/gpu/drm/i915/display/intel_vrr.c
index a88cc9258542..282c49fa5b78 100644
--- a/drivers/gpu/drm/i915/display/intel_vrr.c
+++ b/drivers/gpu/drm/i915/display/intel_vrr.c
@@ -277,6 +277,9 @@ void intel_vrr_compute_vrr_timings(struct intel_crtc_state 
*crtc_state)
 {
        crtc_state->vrr.enable = true;
        crtc_state->mode_flags |= I915_MODE_FLAG_VRR;
+
+       if (intel_vrr_dc_balance_possible(crtc_state))
+               crtc_state->vrr.dc_balance.enable = true;
 }
 
 /*
@@ -662,8 +665,11 @@ void intel_vrr_enable(const struct intel_crtc_state 
*crtc_state)
 
        intel_de_write(display, TRANS_VRR_CTL(display, cpu_transcoder), ctl);
 
-       if (crtc_state->vrr.dc_balance.enable)
+       if (crtc_state->vrr.dc_balance.enable) {
+               intel_de_write(display, TRANS_ADAPTIVE_SYNC_DCB_CTL(display, 
cpu_transcoder),
+                              ADAPTIVE_SYNC_COUNTER_EN);
                intel_pipedmc_dcb_enable(NULL, crtc);
+       }
 }
 
 void intel_vrr_disable(const struct intel_crtc_state *old_crtc_state)
@@ -676,8 +682,10 @@ void intel_vrr_disable(const struct intel_crtc_state 
*old_crtc_state)
        if (!old_crtc_state->vrr.enable)
                return;
 
-       if (old_crtc_state->vrr.dc_balance.enable)
+       if (old_crtc_state->vrr.dc_balance.enable) {
                intel_pipedmc_dcb_disable(NULL, crtc);
+               intel_de_write(display, TRANS_ADAPTIVE_SYNC_DCB_CTL(display, 
cpu_transcoder), 0);
+       }
 
        ctl = trans_vrr_ctl(old_crtc_state);
        if (intel_vrr_always_use_vrr_tg(display))
-- 
2.48.1