On 5/6/2025 8:25 PM, Mitul Golani wrote:
Add function to check if DC Balance possibile on requested PIPE and also validate along with DISPLAY_VER check. Signed-off-by: Mitul Golani <mitulkumar.ajitkumar.gol...@intel.com> --- drivers/gpu/drm/i915/display/intel_vrr.c | 18 +++++++++++++++++- 1 file changed, 17 insertions(+), 1 deletion(-) diff --git a/drivers/gpu/drm/i915/display/intel_vrr.c b/drivers/gpu/drm/i915/display/intel_vrr.c index 1275be16e749..a88cc9258542 100644 --- a/drivers/gpu/drm/i915/display/intel_vrr.c +++ b/drivers/gpu/drm/i915/display/intel_vrr.c @@ -256,6 +256,22 @@ void intel_vrr_compute_cmrr_timings(struct intel_crtc_state *crtc_state) crtc_state->mode_flags |= I915_MODE_FLAG_VRR; }+static+int intel_vrr_dc_balance_possible(const struct intel_crtc_state *crtc_state) +{ + struct intel_display *display = to_intel_display(crtc_state); + struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); + enum pipe pipe = crtc->pipe; + + /* + * FIXME: Currently Firmware supports DC Balancing on PIPE A
I think its good to add documentation for this but FIXME tag is not required.
There is nothing driver can do to fix this. Later if support for other pipes is added, we can remove this.
With the above suggested change: Reviewed-by: Ankit Nautiyal <ankit.k.nauti...@intel.com> Regards, Ankit
+ * and PIPE B. Account those limitation while computing DC + * Balance parameters. + */ + return (HAS_VRR_DC_BALANCE(display) && + ((pipe == PIPE_A) || (pipe == PIPE_B))); +} + static void intel_vrr_compute_vrr_timings(struct intel_crtc_state *crtc_state) { @@ -513,7 +529,7 @@ void intel_vrr_set_transcoder_timings(const struct intel_crtc_state *crtc_state) lower_32_bits(crtc_state->cmrr.cmrr_n)); }- if (HAS_VRR_DC_BALANCE(display) &&+ if (intel_vrr_dc_balance_possible(crtc_state) && (crtc_state->vrr.dc_balance.vmin || crtc_state->vrr.dc_balance.vmax)) { intel_de_write(display, PIPEDMC_DCB_VMIN(pipe), crtc_state->vrr.dc_balance.vmin - 1);
