On Tue, Jun 10, 2025 at 10:06:18PM +0000, Shankar, Uma wrote:
>
>
> > -----Original Message-----
> > From: Intel-gfx <intel-gfx-boun...@lists.freedesktop.org> On Behalf Of Ville
> > Syrjala
> > Sent: Monday, June 9, 2025 7:41 PM
> > To: intel-gfx@lists.freedesktop.org
> > Cc: intel...@lists.freedesktop.org
> > Subject: [PATCH v4 07/21] drm/i915/dmc: Limit PIPEDMC clock gating w/a to
> > just
> > ADL/DG2/MTL
> >
> > From: Ville Syrjälä <ville.syrj...@linux.intel.com>
> >
> > Supposedly nothing post-MTL (even BMG) needs the PIPEDMC clock gating w/a
> > (Wa_16015201720), so don't apply it.
> >
> > TODO: check if the ADL/DG2 "clock gating needed during DMC loading" part
> > is actuall needed, not seeing anything in the docs about it...
>
> Yes ADL does need the WA, you can drop the TODO.
> Display 13.1 ADL: 16015201720 : Clockgating for pipe A DMC and pipe B DMC
> needs to be disabled.
> Bit 12 of register CLKGATE_DIS_PSL_EXT_A (4654Ch) and CLKGATE_DIS_PSL_EXT_B
> (46550h) needs to be set.
I meant the part about also enabling clock gating on pipes C/D
while loading the firmware.
>
> Looks Good to me.
> Reviewed-by: Uma Shankar <uma.shan...@intel.com>
>
> > Signed-off-by: Ville Syrjälä <ville.syrj...@linux.intel.com>
> > ---
> > drivers/gpu/drm/i915/display/intel_dmc.c | 2 +-
> > 1 file changed, 1 insertion(+), 1 deletion(-)
> >
> > diff --git a/drivers/gpu/drm/i915/display/intel_dmc.c
> > b/drivers/gpu/drm/i915/display/intel_dmc.c
> > index a10e56e7cf31..b6ac480f391c 100644
> > --- a/drivers/gpu/drm/i915/display/intel_dmc.c
> > +++ b/drivers/gpu/drm/i915/display/intel_dmc.c
> > @@ -487,7 +487,7 @@ static void mtl_pipedmc_clock_gating_wa(struct
> > intel_display *display)
> >
> > static void pipedmc_clock_gating_wa(struct intel_display *display, bool
> > enable) {
> > - if (DISPLAY_VER(display) >= 14 && enable)
> > + if (display->platform.meteorlake && enable)
> > mtl_pipedmc_clock_gating_wa(display);
> > else if (DISPLAY_VER(display) == 13)
> > adlp_pipedmc_clock_gating_wa(display, enable);
> > --
> > 2.49.0
>
--
Ville Syrjälä
Intel
