On Wed, Jul 16, 2025 at 04:20:28PM +0300, Imre Deak wrote:
> On Thu, Jul 10, 2025 at 11:17:12PM +0300, Ville Syrjala wrote:
> > From: Ville Syrjälä <ville.syrj...@linux.intel.com>
> >
> > On g4x we currently use the 96MHz non-SSC refclk, which can't actually
> > generate an exact 2.7 Gbps link rate. In practice we end up with 2.688
> > Gbps which seems to be close enough to actually work, but link training
> > is currently failing due to miscalculating the DP_LINK_BW value (we
> > calcualte it directly from port_clock which reflects the actual PLL
> > outpout frequency).
> >
> > Ideas how to fix this:
> > - nudge port_clock back up to 270000 during PLL computation/readout
> > - track port_clock and the nominal link rate separately so they might
> > differ a bit
> > - switch to the 100MHz refclk, but that one should be SSC so perhaps
> > not something we want
> >
> > While we ponder about a better solution apply some band aid to the
> > immediate issue of miscalculated DP_LINK_BW value. With this
> > I can again use 2.7 Gbps link rate on g4x.
> >
> > Cc: sta...@vger.kernel.org
> > Fixes: 665a7b04092c ("drm/i915: Feed the DPLL output freq back into
> > crtc_state")
> > Signed-off-by: Ville Syrjälä <ville.syrj...@linux.intel.com>
>
> Reviewed-by: Imre Deak <imre.d...@intel.com>
>
> IIUC, port_clock for g4x is ref * m / n / p, where for DP the fixed
> ref=96000 and m/n/p values from g4x_dpll are used.
>
> Ftr, m = 135, n = 6, p = 8 would give port_clock = 270000, but there's
> no intel_limit for DP, so can't know if these params are within range.
The P divider can only be some multiple of 5.
>
> > ---
> > drivers/gpu/drm/i915/display/intel_dp.c | 6 ++++++
> > 1 file changed, 6 insertions(+)
> >
> > diff --git a/drivers/gpu/drm/i915/display/intel_dp.c
> > b/drivers/gpu/drm/i915/display/intel_dp.c
> > index f48912f308df..7976fec88606 100644
> > --- a/drivers/gpu/drm/i915/display/intel_dp.c
> > +++ b/drivers/gpu/drm/i915/display/intel_dp.c
> > @@ -1606,6 +1606,12 @@ int intel_dp_rate_select(struct intel_dp *intel_dp,
> > int rate)
> > void intel_dp_compute_rate(struct intel_dp *intel_dp, int port_clock,
> > u8 *link_bw, u8 *rate_select)
> > {
> > + struct intel_display *display = to_intel_display(intel_dp);
> > +
> > + /* FIXME g4x can't generate an exact 2.7GHz with the 96MHz non-SSC
> > refclk */
> > + if (display->platform.g4x && port_clock == 268800)
> > + port_clock = 270000;
> > +
> > /* eDP 1.4 rate select method. */
> > if (intel_dp->use_rate_select) {
> > *link_bw = 0;
> > --
> > 2.49.0
> >
--
Ville Syrjälä
Intel
