> -----Original Message-----
> From: Jani Nikula <jani.nik...@linux.intel.com>
> Sent: Tuesday, September 2, 2025 5:03 PM
> To: Shankar, Uma <uma.shan...@intel.com>; intel-gfx@lists.freedesktop.org;
> intel...@lists.freedesktop.org
> Cc: ville.syrj...@linux.intel.com; Govindapillai, Vinod
> <vinod.govindapil...@intel.com>; Shankar, Uma <uma.shan...@intel.com>
> Subject: Re: [PATCH 1/1] drm/i915/display: Remove FBC modulo 4 restriction for
> ADL+
>
> On Tue, 02 Sep 2025, Uma Shankar <uma.shan...@intel.com> wrote:
> > FBC restriction where FBC is disabled for non-modulo 4 plane size
> > (including plane size + yoffset) is fixed from ADL onwards in h/w.
> > WA:22010751166
> >
> > Relax the restriction for the same.
> >
> > v2: Update the macro for display version check (Vinod)
> >
> > Credits-to: Vidya Srinivas <vidya.srini...@intel.com>
>
> Credits-to: is not a trailer we should be using. What does it mean?
>
> The common ways are either:
>
> Suggested-by: N.N.
>
> or a combo of:
>
> Co-developed-by: N.N.
> Signed-off-by: N.N.
>
> Whichever the case may be.
Hi Jani,
It was pointed for clarification so wanted to give the credits for the same.
There were some references of this
sort of usage in upstream tree. Maybe not recommended, I will simply change it
to a text statement and drop the
tag as such.
Regards,
Uma Shankar
>
> BR,
> Jani.
>
>
> > Reviewed-by: Vinod Govindapillai <vinod.govindapil...@intel.com>
> > Signed-off-by: Uma Shankar <uma.shan...@intel.com>
> > ---
> > drivers/gpu/drm/i915/display/intel_fbc.c | 4 ++--
> > 1 file changed, 2 insertions(+), 2 deletions(-)
> >
> > diff --git a/drivers/gpu/drm/i915/display/intel_fbc.c
> > b/drivers/gpu/drm/i915/display/intel_fbc.c
> > index d4c5deff9cbe..9e097ed80bd1 100644
> > --- a/drivers/gpu/drm/i915/display/intel_fbc.c
> > +++ b/drivers/gpu/drm/i915/display/intel_fbc.c
> > @@ -1550,14 +1550,14 @@ static int intel_fbc_check_plane(struct
> intel_atomic_state *state,
> > * having a Y offset that isn't divisible by 4 causes FIFO underrun
> > * and screen flicker.
> > */
> > - if (DISPLAY_VER(display) >= 9 &&
> > + if (IS_DISPLAY_VER(display, 9, 12) &&
> > plane_state->view.color_plane[0].y & 3) {
> > plane_state->no_fbc_reason = "plane start Y offset misaligned";
> > return 0;
> > }
> >
> > /* Wa_22010751166: icl, ehl, tgl, dg1, rkl */
> > - if (DISPLAY_VER(display) >= 11 &&
> > + if (IS_DISPLAY_VER(display, 9, 12) &&
> > (plane_state->view.color_plane[0].y +
> > (drm_rect_height(&plane_state->uapi.src) >> 16)) & 3) {
> > plane_state->no_fbc_reason = "plane end Y offset misaligned";
>
> --
> Jani Nikula, Intel
