From: Ville Syrjälä <[email protected]> Bump the latency for all watermark levels in the 16Gb+ DIMM w/a. The spec does ask us to do it only for level 0, but it seems more sane to bump all the levels. If the actual memory access is slower then the wakeup (WM1+) should also potentially happen earlier.
This also avoids the theoretical case that WM0 would get bumped higher than WM1+. Not that it is likely to happen because the WM0 latency is always significantly lower than the WM1 latency. Signed-off-by: Ville Syrjälä <[email protected]> --- drivers/gpu/drm/i915/display/skl_watermark.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/gpu/drm/i915/display/skl_watermark.c b/drivers/gpu/drm/i915/display/skl_watermark.c index 9eebb908beb8..98a397772678 100644 --- a/drivers/gpu/drm/i915/display/skl_watermark.c +++ b/drivers/gpu/drm/i915/display/skl_watermark.c @@ -3256,7 +3256,7 @@ adjust_wm_latency(struct intel_display *display) * to avoid any underrun. */ if (need_16gb_dimm_wa(display)) - wm[0] += 1; + increase_wm_latency(display, 1); } static void mtl_read_wm_latency(struct intel_display *display) -- 2.49.1
