On 10/17/2025 3:00 PM, Hogander, Jouni wrote:
On Fri, 2025-10-17 at 09:07 +0000, Hogander, Jouni wrote:
On Fri, 2025-10-17 at 10:31 +0530, Ankit Nautiyal wrote:
Introduce a helper to compute the max link wake latency when using
Auxless/Aux wake mechanism for PSR/Panel Replay/LOBF features.
This will be used to compute the minimum guardband so that the link
wake
latencies are accounted and these features work smoothly for higher
refresh rate panels.
Bspec: 70151, 71477
Signed-off-by: Ankit Nautiyal <[email protected]>
---
drivers/gpu/drm/i915/display/intel_psr.c | 12 ++++++++++++
drivers/gpu/drm/i915/display/intel_psr.h | 1 +
2 files changed, 13 insertions(+)
diff --git a/drivers/gpu/drm/i915/display/intel_psr.c
b/drivers/gpu/drm/i915/display/intel_psr.c
index 703e5f6af04c..a8303b669853 100644
--- a/drivers/gpu/drm/i915/display/intel_psr.c
+++ b/drivers/gpu/drm/i915/display/intel_psr.c
@@ -4416,3 +4416,15 @@ void intel_psr_compute_config_late(struct
intel_dp *intel_dp,
intel_psr_set_non_psr_pipes(intel_dp, crtc_state);
}
+
+int intel_psr_min_guardband(struct intel_crtc_state *crtc_state)
+{
+ struct intel_display *display =
to_intel_display(crtc_state);
+ int auxless_wake_lines = crtc_state-
alpm_state.aux_less_wake_lines;
+ int wake_lines = DISPLAY_VER(display) < 20 ?
+ psr2_block_count_lines(crtc_state-
alpm_state.io_wake_lines,
+ crtc_state-
alpm_state.fast_wake_lines) :
+ crtc_state->alpm_state.io_wake_lines;
+
+ return max(auxless_wake_lines, wake_lines);
hmm, now if you add:
if (crtc_state->req_psr2_sdp_prior_scanline)
psr_min_guardband++;
Whatever is the PSR mode it can be enabled what comes to vblank
restrictions and you can drop psr_compute_config_late?
also this should be added to remove psr_compute_config_late:
psr_min_guardband += _intel_psr_min_set_context_latency(crtc_state,
crtc_state->has_panel_replay,
crtc_state->has_sel_update);
No we dont need to use scl here.
We compare the actual optimized guardband based on different features
and then take min(optimized_guardband, intel_vrr_max_vblank_guardband())
intel_vrr_max_vblank_guardband() takes into account if there are SCL
lines, so those are subtracted.
Regards,
Ankit
BR,
Jouni Högander
BR,
Jouni Högander
+}
diff --git a/drivers/gpu/drm/i915/display/intel_psr.h
b/drivers/gpu/drm/i915/display/intel_psr.h
index b17ce312dc37..620b35928832 100644
--- a/drivers/gpu/drm/i915/display/intel_psr.h
+++ b/drivers/gpu/drm/i915/display/intel_psr.h
@@ -85,5 +85,6 @@ bool intel_psr_needs_alpm_aux_less(struct
intel_dp
*intel_dp,
const struct intel_crtc_state
*crtc_state);
void intel_psr_compute_config_late(struct intel_dp *intel_dp,
struct intel_crtc_state
*crtc_state);
+int intel_psr_min_guardband(struct intel_crtc_state *crtc_state);
#endif /* __INTEL_PSR_H__ */
