Define a function to readout hw state for LT Phy PLL which can be used in get_config function call.
Signed-off-by: Suraj Kandpal <[email protected]> Reviewed-by: Arun R Murthy <[email protected]> --- drivers/gpu/drm/i915/display/intel_ddi.c | 14 +++++++++ drivers/gpu/drm/i915/display/intel_lt_phy.c | 33 +++++++++++++++++++++ drivers/gpu/drm/i915/display/intel_lt_phy.h | 3 ++ 3 files changed, 50 insertions(+) diff --git a/drivers/gpu/drm/i915/display/intel_ddi.c b/drivers/gpu/drm/i915/display/intel_ddi.c index 2cbe9fa7135d..fc52fbed72ee 100644 --- a/drivers/gpu/drm/i915/display/intel_ddi.c +++ b/drivers/gpu/drm/i915/display/intel_ddi.c @@ -4246,6 +4246,19 @@ void intel_ddi_get_clock(struct intel_encoder *encoder, &crtc_state->dpll_hw_state); } +static void xe3plpd_ddi_get_config(struct intel_encoder *encoder, + struct intel_crtc_state *crtc_state) +{ + intel_lt_phy_pll_readout_hw_state(encoder, crtc_state, &crtc_state->dpll_hw_state.ltpll); + + if (crtc_state->dpll_hw_state.ltpll.tbt_mode) + crtc_state->port_clock = intel_mtl_tbt_calc_port_clock(encoder); + else + crtc_state->port_clock = + intel_lt_phy_calc_port_clock(encoder, crtc_state); + intel_ddi_get_config(encoder, crtc_state); +} + static void mtl_ddi_get_config(struct intel_encoder *encoder, struct intel_crtc_state *crtc_state) { @@ -5241,6 +5254,7 @@ void intel_ddi_init(struct intel_display *display, encoder->enable_clock = intel_xe3plpd_pll_enable; encoder->disable_clock = intel_xe3plpd_pll_disable; encoder->port_pll_type = intel_mtl_port_pll_type; + encoder->get_config = xe3plpd_ddi_get_config; } else if (DISPLAY_VER(display) >= 14) { encoder->enable_clock = intel_mtl_pll_enable; encoder->disable_clock = intel_mtl_pll_disable; diff --git a/drivers/gpu/drm/i915/display/intel_lt_phy.c b/drivers/gpu/drm/i915/display/intel_lt_phy.c index 45130fdc6273..4788dc89b968 100644 --- a/drivers/gpu/drm/i915/display/intel_lt_phy.c +++ b/drivers/gpu/drm/i915/display/intel_lt_phy.c @@ -1869,6 +1869,39 @@ intel_lt_phy_pll_compare_hw_state(const struct intel_lt_phy_pll_state *a, return true; } +void intel_lt_phy_pll_readout_hw_state(struct intel_encoder *encoder, + const struct intel_crtc_state *crtc_state, + struct intel_lt_phy_pll_state *pll_state) +{ + u8 owned_lane_mask; + u8 lane; + intel_wakeref_t wakeref; + int i, j, k; + + pll_state->tbt_mode = intel_tc_port_in_tbt_alt_mode(enc_to_dig_port(encoder)); + if (pll_state->tbt_mode) + return; + + owned_lane_mask = intel_lt_phy_get_owned_lane_mask(encoder); + lane = owned_lane_mask & INTEL_LT_PHY_LANE0 ? : INTEL_LT_PHY_LANE1; + wakeref = intel_lt_phy_transaction_begin(encoder); + + pll_state->config[0] = intel_lt_phy_read(encoder, lane, LT_PHY_VDR_0_CONFIG); + pll_state->config[1] = intel_lt_phy_read(encoder, INTEL_LT_PHY_LANE0, LT_PHY_VDR_1_CONFIG); + pll_state->config[2] = intel_lt_phy_read(encoder, lane, LT_PHY_VDR_2_CONFIG); + + for (i = 0; i <= 12; i++) { + for (j = 3, k = 0; j >= 0; j--, k++) + pll_state->data[i][k] = + intel_lt_phy_read(encoder, INTEL_LT_PHY_LANE0, + LT_PHY_VDR_X_DATAY(i, j)); + } + + pll_state->clock = + intel_lt_phy_calc_port_clock(encoder, crtc_state); + intel_lt_phy_transaction_end(encoder, wakeref); +} + void intel_xe3plpd_pll_enable(struct intel_encoder *encoder, const struct intel_crtc_state *crtc_state) { diff --git a/drivers/gpu/drm/i915/display/intel_lt_phy.h b/drivers/gpu/drm/i915/display/intel_lt_phy.h index e93e5becc316..dd8cbb151b23 100644 --- a/drivers/gpu/drm/i915/display/intel_lt_phy.h +++ b/drivers/gpu/drm/i915/display/intel_lt_phy.h @@ -28,6 +28,9 @@ void intel_lt_phy_dump_hw_state(struct intel_display *display, bool intel_lt_phy_pll_compare_hw_state(const struct intel_lt_phy_pll_state *a, const struct intel_lt_phy_pll_state *b); +void intel_lt_phy_pll_readout_hw_state(struct intel_encoder *encoder, + const struct intel_crtc_state *crtc_state, + struct intel_lt_phy_pll_state *pll_state); void intel_xe3plpd_pll_enable(struct intel_encoder *encoder, const struct intel_crtc_state *crtc_state); void intel_xe3plpd_pll_disable(struct intel_encoder *encoder); -- 2.34.1
