On Mon, Nov 03, 2025 at 02:18:09PM -0300, Gustavo Sousa wrote: > From: Ravi Kumar Vodapalli <[email protected]> > > Xe3p_LPD updated fields of registers MBUS_CTL and DBUF_CTL to > accommodate for higher MDCLK:CDCLK ratios. Update the code to use the > new fields. > > The field MBUS_TRANSLATION_THROTTLE_MIN_MASK was changed from range > [15:13] to [16:13]. Since bit 16 is not reserved in previous display > IPs and already used for something else, we can't simply extend the mask > definition to include it, but rather define an Xe3p-specific mask and > select the correct one to use based on the IP version. > > Similarly, DBUF_MIN_TRACKER_STATE_SERVICE_MASK was changed from range > [18:16] to [20:16]. For the same reasons stated above, it needs a > Xe3p-specific mask definition. > > v2: > - Keep definitions in the same line (i.e. without line continuation > breaks) for better readability. (Jani) > v3: > - Keep mask fields sorted by the upper limit. (Matt) > - Extend commit message to indicate why we need Xe3p-specific > definitions of the masks instead of just extending the existing > ones. (Matt) > > Bspec: 68868, 68872 > Cc: Jani Nikula <[email protected]> > Cc: Matt Roper <[email protected]> > Signed-off-by: Ravi Kumar Vodapalli <[email protected]> > Signed-off-by: Gustavo Sousa <[email protected]>
Reviewed-by: Matt Roper <[email protected]> > --- > drivers/gpu/drm/i915/display/skl_watermark.c | 16 +++++-- > drivers/gpu/drm/i915/display/skl_watermark_regs.h | 52 > ++++++++++++----------- > 2 files changed, 40 insertions(+), 28 deletions(-) > > diff --git a/drivers/gpu/drm/i915/display/skl_watermark.c > b/drivers/gpu/drm/i915/display/skl_watermark.c > index c888b0896d89..d20c88ebe919 100644 > --- a/drivers/gpu/drm/i915/display/skl_watermark.c > +++ b/drivers/gpu/drm/i915/display/skl_watermark.c > @@ -3479,7 +3479,10 @@ void intel_dbuf_mdclk_cdclk_ratio_update(struct > intel_display *display, > if (!HAS_MBUS_JOINING(display)) > return; > > - if (DISPLAY_VER(display) >= 20) > + if (DISPLAY_VER(display) >= 35) > + intel_de_rmw(display, MBUS_CTL, > XE3P_MBUS_TRANSLATION_THROTTLE_MIN_MASK, > + XE3P_MBUS_TRANSLATION_THROTTLE_MIN(ratio - 1)); > + else if (DISPLAY_VER(display) >= 20) > intel_de_rmw(display, MBUS_CTL, > MBUS_TRANSLATION_THROTTLE_MIN_MASK, > MBUS_TRANSLATION_THROTTLE_MIN(ratio - 1)); > > @@ -3490,9 +3493,14 @@ void intel_dbuf_mdclk_cdclk_ratio_update(struct > intel_display *display, > ratio, str_yes_no(joined_mbus)); > > for_each_dbuf_slice(display, slice) > - intel_de_rmw(display, DBUF_CTL_S(slice), > - DBUF_MIN_TRACKER_STATE_SERVICE_MASK, > - DBUF_MIN_TRACKER_STATE_SERVICE(ratio - 1)); > + if (DISPLAY_VER(display) >= 35) > + intel_de_rmw(display, DBUF_CTL_S(slice), > + XE3P_DBUF_MIN_TRACKER_STATE_SERVICE_MASK, > + XE3P_DBUF_MIN_TRACKER_STATE_SERVICE(ratio > - 1)); > + else > + intel_de_rmw(display, DBUF_CTL_S(slice), > + DBUF_MIN_TRACKER_STATE_SERVICE_MASK, > + DBUF_MIN_TRACKER_STATE_SERVICE(ratio - 1)); > } > > static void intel_dbuf_mdclk_min_tracker_update(struct intel_atomic_state > *state) > diff --git a/drivers/gpu/drm/i915/display/skl_watermark_regs.h > b/drivers/gpu/drm/i915/display/skl_watermark_regs.h > index c5572fc0e847..abf56ac31105 100644 > --- a/drivers/gpu/drm/i915/display/skl_watermark_regs.h > +++ b/drivers/gpu/drm/i915/display/skl_watermark_regs.h > @@ -32,16 +32,18 @@ > #define MBUS_BBOX_CTL_S1 _MMIO(0x45040) > #define MBUS_BBOX_CTL_S2 _MMIO(0x45044) > > -#define MBUS_CTL _MMIO(0x4438C) > -#define MBUS_JOIN REG_BIT(31) > -#define MBUS_HASHING_MODE_MASK REG_BIT(30) > -#define MBUS_HASHING_MODE_2x2 > REG_FIELD_PREP(MBUS_HASHING_MODE_MASK, 0) > -#define MBUS_HASHING_MODE_1x4 > REG_FIELD_PREP(MBUS_HASHING_MODE_MASK, 1) > -#define MBUS_JOIN_PIPE_SELECT_MASK REG_GENMASK(28, 26) > -#define MBUS_JOIN_PIPE_SELECT(pipe) > REG_FIELD_PREP(MBUS_JOIN_PIPE_SELECT_MASK, pipe) > -#define MBUS_JOIN_PIPE_SELECT_NONE MBUS_JOIN_PIPE_SELECT(7) > -#define MBUS_TRANSLATION_THROTTLE_MIN_MASK REG_GENMASK(15, 13) > -#define MBUS_TRANSLATION_THROTTLE_MIN(val) > REG_FIELD_PREP(MBUS_TRANSLATION_THROTTLE_MIN_MASK, val) > +#define MBUS_CTL _MMIO(0x4438C) > +#define MBUS_JOIN REG_BIT(31) > +#define MBUS_HASHING_MODE_MASK REG_BIT(30) > +#define MBUS_HASHING_MODE_2x2 > REG_FIELD_PREP(MBUS_HASHING_MODE_MASK, 0) > +#define MBUS_HASHING_MODE_1x4 > REG_FIELD_PREP(MBUS_HASHING_MODE_MASK, 1) > +#define MBUS_JOIN_PIPE_SELECT_MASK REG_GENMASK(28, 26) > +#define MBUS_JOIN_PIPE_SELECT(pipe) > REG_FIELD_PREP(MBUS_JOIN_PIPE_SELECT_MASK, pipe) > +#define MBUS_JOIN_PIPE_SELECT_NONE MBUS_JOIN_PIPE_SELECT(7) > +#define XE3P_MBUS_TRANSLATION_THROTTLE_MIN_MASK REG_GENMASK(16, 13) > +#define XE3P_MBUS_TRANSLATION_THROTTLE_MIN(val) > REG_FIELD_PREP(XE3P_MBUS_TRANSLATION_THROTTLE_MIN_MASK, val) > +#define MBUS_TRANSLATION_THROTTLE_MIN_MASK REG_GENMASK(15, 13) > +#define MBUS_TRANSLATION_THROTTLE_MIN(val) > REG_FIELD_PREP(MBUS_TRANSLATION_THROTTLE_MIN_MASK, val) > > /* > * The below are numbered starting from "S1" on gen11/gen12, but starting > @@ -51,20 +53,22 @@ > * way things will be named by the hardware team going forward, plus it's > more > * consistent with how most of the rest of our registers are named. > */ > -#define _DBUF_CTL_S0 0x45008 > -#define _DBUF_CTL_S1 0x44FE8 > -#define _DBUF_CTL_S2 0x44300 > -#define _DBUF_CTL_S3 0x44304 > -#define DBUF_CTL_S(slice) _MMIO(_PICK(slice, \ > - _DBUF_CTL_S0, \ > - _DBUF_CTL_S1, \ > - _DBUF_CTL_S2, \ > - _DBUF_CTL_S3)) > -#define DBUF_POWER_REQUEST REG_BIT(31) > -#define DBUF_POWER_STATE REG_BIT(30) > -#define DBUF_TRACKER_STATE_SERVICE_MASK REG_GENMASK(23, 19) > -#define DBUF_TRACKER_STATE_SERVICE(x) > REG_FIELD_PREP(DBUF_TRACKER_STATE_SERVICE_MASK, x) > -#define DBUF_MIN_TRACKER_STATE_SERVICE_MASK REG_GENMASK(18, 16) /* ADL-P+ */ > +#define _DBUF_CTL_S0 0x45008 > +#define _DBUF_CTL_S1 0x44FE8 > +#define _DBUF_CTL_S2 0x44300 > +#define _DBUF_CTL_S3 0x44304 > +#define DBUF_CTL_S(slice) _MMIO(_PICK(slice, \ > + > _DBUF_CTL_S0, \ > + > _DBUF_CTL_S1, \ > + > _DBUF_CTL_S2, \ > + > _DBUF_CTL_S3)) > +#define DBUF_POWER_REQUEST REG_BIT(31) > +#define DBUF_POWER_STATE REG_BIT(30) > +#define DBUF_TRACKER_STATE_SERVICE_MASK REG_GENMASK(23, 19) > +#define DBUF_TRACKER_STATE_SERVICE(x) > REG_FIELD_PREP(DBUF_TRACKER_STATE_SERVICE_MASK, x) > +#define XE3P_DBUF_MIN_TRACKER_STATE_SERVICE_MASK REG_GENMASK(20, 16) > +#define XE3P_DBUF_MIN_TRACKER_STATE_SERVICE(x) > REG_FIELD_PREP(XE3P_DBUF_MIN_TRACKER_STATE_SERVICE_MASK, x) > +#define DBUF_MIN_TRACKER_STATE_SERVICE_MASK REG_GENMASK(18, 16) /* > ADL-P+ */ > #define DBUF_MIN_TRACKER_STATE_SERVICE(x) > REG_FIELD_PREP(DBUF_MIN_TRACKER_STATE_SERVICE_MASK, x) /* ADL-P+ */ > > #define MTL_LATENCY_LP0_LP1 _MMIO(0x45780) > > -- > 2.51.0 > -- Matt Roper Graphics Software Engineer Linux GPU Platform Enablement Intel Corporation
