On Mon, Nov 03, 2025 at 02:18:11PM -0300, Gustavo Sousa wrote: > When reading memory latencies for watermark calculations, previous > display releases instructed to apply an adjustment of adding a certain > value (e.g. 6us) to all levels when the level 0's memory latency read > from hardware was zero. > > For Xe3p_LPD, the instruction is to always use 6us for level 0 and to > add that value to the other levels. Add the necessary code in > sanitize_wm_latency() so that WaWmMemoryReadLatency is always applied > for Xe3p_LPD and beyond. > > v2: > - Rebased after addition of prep patch "drm/i915/wm: Reorder > adjust_wm_latency() for Xe3_LPD" (dropped in v3). > v3: > - Back to the simpler approach of doing the 'wm[0] = 0' step without > modifying the rest of the code, and that inside > sanitize_wm_latency(). (Matt Roper, Ville) > > Bspec: 68986, 69126 > Cc: Matt Atwood <[email protected]> > Cc: Matt Roper <[email protected]> > Cc: Ville Syrjälä <[email protected]> > Signed-off-by: Gustavo Sousa <[email protected]>
Reviewed-by: Matt Roper <[email protected]> > --- > drivers/gpu/drm/i915/display/skl_watermark.c | 7 +++++++ > 1 file changed, 7 insertions(+) > > diff --git a/drivers/gpu/drm/i915/display/skl_watermark.c > b/drivers/gpu/drm/i915/display/skl_watermark.c > index e13324af7afb..ed55fe84e930 100644 > --- a/drivers/gpu/drm/i915/display/skl_watermark.c > +++ b/drivers/gpu/drm/i915/display/skl_watermark.c > @@ -3184,6 +3184,13 @@ static void sanitize_wm_latency(struct intel_display > *display) > u16 *wm = display->wm.skl_latency; > int level, num_levels = display->wm.num_levels; > > + /* > + * Xe3p and beyond should ignore level 0's reported latency and > + * always apply WaWmMemoryReadLatency logic. > + */ > + if (DISPLAY_VER(display) >= 35) > + wm[0] = 0; > + > /* > * If a level n (n > 1) has a 0us latency, all levels m (m >= n) > * need to be disabled. We make sure to sanitize the values out > > -- > 2.51.0 > -- Matt Roper Graphics Software Engineer Linux GPU Platform Enablement Intel Corporation
