On Tue, Nov 18, 2025 at 06:38:13AM +0200, Suraj Kandpal wrote:
> [...]
> > +static const struct intel_dpll_funcs mtl_tbt_pll_funcs = {
> > + .enable = mtl_tbt_pll_enable,
> > + .disable = mtl_tbt_pll_disable,
> > + .get_hw_state = intel_mtl_tbt_pll_readout_hw_state,
> > + .get_freq = mtl_tbt_pll_get_freq,
> > +};
> > +
> > static const struct dpll_info mtl_plls[] = {
> > { .name = "DPLL 0", .funcs = &mtl_pll_funcs, .id = DPLL_ID_ICL_DPLL0, },
> > { .name = "DPLL 1", .funcs = &mtl_pll_funcs, .id = DPLL_ID_ICL_DPLL1, },
> > - /* TODO: Add TBT PLL */
> > + { .name = "TBT PLL", .funcs = &mtl_tbt_pll_funcs, .id =
> > DPLL_ID_ICL_TBTPLL,
> > + .is_alt_port_dpll = true, .always_on = true },
> > { .name = "TC PLL 1", .funcs = &mtl_pll_funcs, .id =
> > DPLL_ID_ICL_MGPLL1, },
> > { .name = "TC PLL 2", .funcs = &mtl_pll_funcs, .id =
> > DPLL_ID_ICL_MGPLL2, },
> > { .name = "TC PLL 3", .funcs = &mtl_pll_funcs, .id =
> > DPLL_ID_ICL_MGPLL3, },
> > @@ -4470,7 +4502,8 @@ static int
> > mtl_compute_tc_phy_dplls(struct intel_atomic_state *state,
> > struct icl_port_dpll *port_dpll;
> > int ret;
> >
> > - /* TODO: Add state calculation for TBT PLL */
> > + port_dpll = &crtc_state->icl_port_dplls[ICL_PORT_DPLL_DEFAULT];
>
> Should this be DPLL_DEFAULT or MG_PHY
The Thunderbolt PLL state should be stored to the ICL_PORT_DPLL_DEFAULT
port PLL index, as above.
>
> Regards,
> Suraj Kandpal
>
> > + intel_mtl_tbt_pll_calc_state(&port_dpll->hw_state);
> >
> > port_dpll = &crtc_state->icl_port_dplls[ICL_PORT_DPLL_MG_PHY];
> > ret = intel_cx0pll_calc_state(crtc_state, encoder,
> > &port_dpll->hw_state);
> > --
> > 2.34.1
>
