> -----Original Message-----
> From: Jani Nikula <[email protected]>
> Sent: Wednesday, December 10, 2025 2:25 PM
> To: Manna, Animesh <[email protected]>; intel-
> [email protected]; [email protected]
> Cc: Manna, Animesh <[email protected]>
> Subject: Re: [PATCH] drm/i915/display: Panel Replay BW optimization for
> DP2.0 tunneling
>
> On Wed, 10 Dec 2025, Animesh Manna <[email protected]> wrote:
> > Unused bandwidth can be used by external display agents for Panel
> > Replay enabled DP panel during idleness with link on. Enable source to
> > replace dummy data from the display with data from another agent by
> > programming TRANS_DP2_CTL [Panel Replay Tunneling Enable].
> >
> > Bspec: 68920
> > Signed-off-by: Animesh Manna <[email protected]>
> > ---
> > .../gpu/drm/i915/display/intel_display_regs.h | 1 +
> > drivers/gpu/drm/i915/display/intel_psr.c | 23 +++++++++++++++++++
> > 2 files changed, 24 insertions(+)
> >
> > diff --git a/drivers/gpu/drm/i915/display/intel_display_regs.h
> > b/drivers/gpu/drm/i915/display/intel_display_regs.h
> > index 9e0d853f4b61..b6fc249a9f09 100644
> > --- a/drivers/gpu/drm/i915/display/intel_display_regs.h
> > +++ b/drivers/gpu/drm/i915/display/intel_display_regs.h
> > @@ -2051,6 +2051,7 @@
> > #define TRANS_DP2_CTL(trans) _MMIO_TRANS(trans,
> _TRANS_DP2_CTL_A, _TRANS_DP2_CTL_B)
> > #define TRANS_DP2_128B132B_CHANNEL_CODING REG_BIT(31)
> > #define TRANS_DP2_PANEL_REPLAY_ENABLE REG_BIT(30)
> > +#define TRANS_DP2_PR_TUNNELING_ENABLE REG_BIT(26)
> > #define TRANS_DP2_DEBUG_ENABLE REG_BIT(23)
> >
> > #define _TRANS_DP2_VFREQHIGH_A 0x600a4
> > diff --git a/drivers/gpu/drm/i915/display/intel_psr.c
> > b/drivers/gpu/drm/i915/display/intel_psr.c
> > index 2a378a5adc59..d0a01a08299e 100644
> > --- a/drivers/gpu/drm/i915/display/intel_psr.c
> > +++ b/drivers/gpu/drm/i915/display/intel_psr.c
> > @@ -44,6 +44,7 @@
> > #include "intel_dmc.h"
> > #include "intel_dp.h"
> > #include "intel_dp_aux.h"
> > +#include "intel_dp_tunnel.h"
> > #include "intel_dsb.h"
> > #include "intel_frontbuffer.h"
> > #include "intel_hdmi.h"
> > @@ -2152,6 +2153,25 @@ static bool psr_interrupt_error_check(struct
> intel_dp *intel_dp)
> > return true;
> > }
> >
> > +static void intel_psr_set_pr_bw_optimization(struct intel_dp
> > +*intel_dp) {
> > + struct intel_display *display = to_intel_display(intel_dp);
> > + u8 val;
> > +
> > + if (DISPLAY_VER(display) < 35)
> > + return;
> > +
> > + if (!intel_dp_tunnel_bw_alloc_is_enabled(intel_dp))
> > + return;
> > +
> > + drm_dp_dpcd_readb(&intel_dp->aux, DP_TUNNELING_CAPABILITIES,
> &val);
> > + if (!(val & DP_PANEL_REPLAY_OPTIMIZATION_SUPPORT))
> > + return;
> > +
> > + intel_de_rmw(display, TRANS_DP2_CTL(intel_dp->psr.transcoder), 0,
> > + TRANS_DP2_PR_TUNNELING_ENABLE); }
>
> Why is this so separated from dg2_activate_panel_replay()?
I felt this feature more leaning towards DP tunneling, so kept outside of
dg2_activate_panel_replay().
But this is just after intel_psr_activate().
Regards,
Animesh
>
> > +
> > static void intel_psr_enable_locked(struct intel_dp *intel_dp,
> > const struct intel_crtc_state *crtc_state)
> > {
> @@ -2221,6
> > +2241,9 @@ static void intel_psr_enable_locked(struct intel_dp *intel_dp,
> > intel_dp->psr.link_ok = true;
> >
> > intel_psr_activate(intel_dp);
> > +
> > + if (!intel_dp_is_edp(intel_dp) && intel_dp-
> >psr.panel_replay_enabled)
> > + intel_psr_set_pr_bw_optimization(intel_dp);
> > }
> >
> > static void intel_psr_exit(struct intel_dp *intel_dp)
>
> --
> Jani Nikula, Intel
