On Tue, Apr 22, 2014 at 08:17:52PM +0300, Jani Nikula wrote: > Most likely the minimums for both should be enough for enabling the > native resolution on the eDP. > > Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=73539 > Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=76711 > Signed-off-by: Jani Nikula <[email protected]>
Tested-by: Markus Blank-Burian <[email protected]> > --- > drivers/gpu/drm/i915/intel_dp.c | 23 ++++++++++++++++------- > 1 file changed, 16 insertions(+), 7 deletions(-) > > diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c > index 80e5598d66ed..c613da9cb1a9 100644 > --- a/drivers/gpu/drm/i915/intel_dp.c > +++ b/drivers/gpu/drm/i915/intel_dp.c > @@ -764,8 +764,10 @@ intel_dp_compute_config(struct intel_encoder *encoder, > struct intel_crtc *intel_crtc = encoder->new_crtc; > struct intel_connector *intel_connector = intel_dp->attached_connector; > int lane_count, clock; > + int min_lane_count = 1; > int max_lane_count = drm_dp_max_lane_count(intel_dp->dpcd); > /* Conveniently, the link BW constants become indices with a shift...*/ > + int min_clock = 0; > int max_clock = intel_dp_max_link_bw(intel_dp) >> 3; > int bpp, mode_rate; > static int bws[] = { DP_LINK_BW_1_62, DP_LINK_BW_2_7, DP_LINK_BW_5_4 }; > @@ -798,19 +800,26 @@ intel_dp_compute_config(struct intel_encoder *encoder, > /* Walk through all bpp values. Luckily they're all nicely spaced with 2 > * bpc in between. */ > bpp = pipe_config->pipe_bpp; > - if (is_edp(intel_dp) && dev_priv->vbt.edp_bpp && > - dev_priv->vbt.edp_bpp < bpp) { > - DRM_DEBUG_KMS("clamping bpp for eDP panel to BIOS-provided > %i\n", > - dev_priv->vbt.edp_bpp); > - bpp = dev_priv->vbt.edp_bpp; > + if (is_edp(intel_dp)) { > + if (dev_priv->vbt.edp_bpp && dev_priv->vbt.edp_bpp < bpp) { > + DRM_DEBUG_KMS("clamping bpp for eDP panel to > BIOS-provided %i\n", > + dev_priv->vbt.edp_bpp); > + bpp = dev_priv->vbt.edp_bpp; > + } > + > + if (dev_priv->vbt.edp_lanes) > + min_lane_count = min(dev_priv->vbt.edp_lanes, > + max_lane_count); > + if (dev_priv->vbt.edp_rate) > + min_clock = min(dev_priv->vbt.edp_rate >> 3, max_clock); > } > > for (; bpp >= 6*3; bpp -= 2*3) { > mode_rate = intel_dp_link_required(adjusted_mode->crtc_clock, > bpp); > > - for (lane_count = 1; lane_count <= max_lane_count; lane_count > <<= 1) { > - for (clock = 0; clock <= max_clock; clock++) { > + for (lane_count = min_lane_count; lane_count <= max_lane_count; > lane_count <<= 1) { > + for (clock = min_clock; clock <= max_clock; clock++) { > link_clock = > drm_dp_bw_code_to_link_rate(bws[clock]); > link_avail = intel_dp_max_data_rate(link_clock, > lane_count); > -- > 1.9.1 > > _______________________________________________ > Intel-gfx mailing list > [email protected] > http://lists.freedesktop.org/mailman/listinfo/intel-gfx -- Daniel Vetter Software Engineer, Intel Corporation +41 (0) 79 365 57 48 - http://blog.ffwll.ch _______________________________________________ Intel-gfx mailing list [email protected] http://lists.freedesktop.org/mailman/listinfo/intel-gfx
