Previous fix enabled LSC chicken bit FORCE_1_SUB_MESSAGE_PER_FRAGMENT.
This caused side effects on 128EU SKUs. Updated solution limits SLM
allocation to 96KB which is done at UMD to avoid these issues and
ensure stable behavior.
Bspec: 54833
Fixes: 645cc0b9d972 ("drm/i915/dg2: Add initial gt/ctx/engine workarounds")
Signed-off-by: Jia Yao <[email protected]>
Cc: Alex Zuo <[email protected]>
Cc: Shuicheng Lin <[email protected]>
Cc: Xin Wang <[email protected]>
Cc: [email protected]
Cc: Matt Roper <[email protected]>
---
drivers/gpu/drm/i915/gt/intel_workarounds.c | 4 ----
1 file changed, 4 deletions(-)
diff --git a/drivers/gpu/drm/i915/gt/intel_workarounds.c
b/drivers/gpu/drm/i915/gt/intel_workarounds.c
index ece88c612e27..abb47c65f43a 100644
--- a/drivers/gpu/drm/i915/gt/intel_workarounds.c
+++ b/drivers/gpu/drm/i915/gt/intel_workarounds.c
@@ -2866,10 +2866,6 @@ general_render_compute_wa_init(struct intel_engine_cs
*engine, struct i915_wa_li
MAXREQS_PER_BANK,
REG_FIELD_PREP(MAXREQS_PER_BANK, 2));
- /* Wa_22013059131:dg2 */
- wa_mcr_write_or(wal, LSC_CHICKEN_BIT_0,
- FORCE_1_SUB_MESSAGE_PER_FRAGMENT);
-
/*
* Wa_22012654132
*
--
2.34.1
