On 12-12-2025 13:07, Hogander, Jouni wrote:
On Tue, 2025-12-09 at 17:03 +0530, Dibin Moolakadan Subrahmanian wrote:
if DC3CO allowed set PR_ALPM_CTL_USE_DC3CO_IDLE_PROTOCOL
in ALPM_CTL and update dc3co_source
Signed-off-by: Dibin Moolakadan Subrahmanian
<[email protected]>
---
drivers/gpu/drm/i915/display/intel_alpm.c | 4 ++++
drivers/gpu/drm/i915/display/intel_psr_regs.h | 1 +
2 files changed, 5 insertions(+)
diff --git a/drivers/gpu/drm/i915/display/intel_alpm.c
b/drivers/gpu/drm/i915/display/intel_alpm.c
index 7ce8c674bb03..28a95f6ddfab 100644
--- a/drivers/gpu/drm/i915/display/intel_alpm.c
+++ b/drivers/gpu/drm/i915/display/intel_alpm.c
@@ -347,6 +347,10 @@ static void lnl_alpm_configure(struct intel_dp
*intel_dp,
alpm_ctl |= ALPM_CTL_ALPM_ENTRY_CHECK(crtc_state-
alpm_state.check_entry_lines);
+ if (intel_dc3co_allowed(display)) {
+ alpm_ctl |= (PR_ALPM_CTL_USE_DC3CO_IDLE_PROTOCOL);
+ intel_dc3co_source_set(display, DC3CO_SOURCE_ALPM);
This source concept is generally confusing. More specifically
DC3CO_SOURCE_ALPM I don't understand:
PSR and LOBF are methods to allow switching link off. ALPM is a method
to switch the link off. DC3CO and DC6 are Display power saving states
which are possible as the link is switched off.
Thank you for comments , I want to track the reason for enabling DC3CO.
I will remove DC3CO_SOURCE_ALPM as you pointed, but want to keep
DC3CO_REASON_PSR2 and DC3CO_REASON_LOBF .
BR,
Jouni Högander
+ }
intel_de_write(display, ALPM_CTL(display, cpu_transcoder),
alpm_ctl);
mutex_unlock(&intel_dp->alpm.lock);
}
diff --git a/drivers/gpu/drm/i915/display/intel_psr_regs.h
b/drivers/gpu/drm/i915/display/intel_psr_regs.h
index 8afbf5a38335..16a9e3af198d 100644
--- a/drivers/gpu/drm/i915/display/intel_psr_regs.h
+++ b/drivers/gpu/drm/i915/display/intel_psr_regs.h
@@ -268,6 +268,7 @@
#define _PR_ALPM_CTL_A 0x60948
#define PR_ALPM_CTL(dev_priv, tran) _MMIO_TRANS2(dev_priv, tran,
_PR_ALPM_CTL_A)
+#define
PR_ALPM_CTL_USE_DC3CO_IDLE_PROTOCOL BIT(7)
#define
PR_ALPM_CTL_ALLOW_LINK_OFF_BETWEEN_AS_SDP_AND_SU BIT(6)
#define
PR_ALPM_CTL_RFB_UPDATE_CONTROL BIT(5)
#define
PR_ALPM_CTL_AS_SDP_TRANSMISSION_IN_ACTIVE_DISABLE BIT(4)
