Add explicit handling for DC3CO in the dc_off power well sequencing. Introduce xe3lpd_enable_dc3co() and wire it into the dc_off power enable flow. gen9_disable_dc_states() is also updated to disable the corresponding DMC wakelock when transitioning out of DC3CO.
Signed-off-by: Dibin Moolakadan Subrahmanian <[email protected]> --- .../drm/i915/display/intel_display_power_well.c | 16 +++++++++++++++- 1 file changed, 15 insertions(+), 1 deletion(-) diff --git a/drivers/gpu/drm/i915/display/intel_display_power_well.c b/drivers/gpu/drm/i915/display/intel_display_power_well.c index 6f62a4420f6e..6d8d9d7b7d0a 100644 --- a/drivers/gpu/drm/i915/display/intel_display_power_well.c +++ b/drivers/gpu/drm/i915/display/intel_display_power_well.c @@ -821,6 +821,13 @@ void gen9_set_dc_state(struct intel_display *display, u32 state) power_domains->dc_state = val & mask; } +static void xe3lpd_enable_dc3co(struct intel_display *display) +{ + drm_dbg_kms(display->drm, "Enabling DC3CO\n"); + intel_dmc_wl_enable(display, DC_STATE_EN_UPTO_DC3CO); + gen9_set_dc_state(display, DC_STATE_EN_UPTO_DC3CO); +} + static void assert_can_enable_dc5(struct intel_display *display) { enum i915_power_well_id high_pg; @@ -1009,9 +1016,13 @@ void gen9_disable_dc_states(struct intel_display *display) } if (old_state == DC_STATE_EN_UPTO_DC5 || - old_state == DC_STATE_EN_UPTO_DC6) + old_state == DC_STATE_EN_UPTO_DC6 || + old_state == DC_STATE_EN_UPTO_DC3CO) intel_dmc_wl_disable(display); + if (old_state == DC_STATE_EN_UPTO_DC3CO) + return; + intel_cdclk_get_cdclk(display, &cdclk_config); /* Can't read out voltage_level so can't use intel_cdclk_changed() */ drm_WARN_ON(display->drm, @@ -1047,6 +1058,9 @@ static void gen9_dc_off_power_well_disable(struct intel_display *display, return; switch (power_domains->target_dc_state) { + case DC_STATE_EN_UPTO_DC3CO: + xe3lpd_enable_dc3co(display); + break; case DC_STATE_EN_UPTO_DC6: skl_enable_dc6(display); break; -- 2.43.0
