[PATCH 04/13] drm/i915/cx0: Fix HDMI FRL clock rates

[Mika Kahola]

HDMI FRL clock rates are incorrectly defined. Fix these
rates.

Signed-off-by: Mika Kahola <mika.kah...@intel.com>
---
 drivers/gpu/drm/i915/display/intel_cx0_phy.c | 10 +++++-----
 1 file changed, 5 insertions(+), 5 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_cx0_phy.c 
b/drivers/gpu/drm/i915/display/intel_cx0_phy.c
index 4cf4b49d1cab..363df72fd01d 100644
--- a/drivers/gpu/drm/i915/display/intel_cx0_phy.c
+++ b/drivers/gpu/drm/i915/display/intel_cx0_phy.c
@@ -1890,7 +1890,7 @@ static const struct intel_c20pll_state mtl_c20_hdmi_594 = 
{
 };
 
 static const struct intel_c20pll_state mtl_c20_hdmi_300 = {
-       .clock = 3000000,
+       .clock = 300000,
        .tx = {  0xbe98, /* tx cfg0 */
                  0x8800, /* tx cfg1 */
                  0x0000, /* tx cfg2 */
@@ -1915,7 +1915,7 @@ static const struct intel_c20pll_state mtl_c20_hdmi_300 = 
{
 };
 
 static const struct intel_c20pll_state mtl_c20_hdmi_600 = {
-       .clock = 6000000,
+       .clock = 600000,
        .tx = {  0xbe98, /* tx cfg0 */
                  0x8800, /* tx cfg1 */
                  0x0000, /* tx cfg2 */
@@ -1940,7 +1940,7 @@ static const struct intel_c20pll_state mtl_c20_hdmi_600 = 
{
 };
 
 static const struct intel_c20pll_state mtl_c20_hdmi_800 = {
-       .clock = 8000000,
+       .clock = 800000,
        .tx = {  0xbe98, /* tx cfg0 */
                  0x8800, /* tx cfg1 */
                  0x0000, /* tx cfg2 */
@@ -1965,7 +1965,7 @@ static const struct intel_c20pll_state mtl_c20_hdmi_800 = 
{
 };
 
 static const struct intel_c20pll_state mtl_c20_hdmi_1000 = {
-       .clock = 10000000,
+       .clock = 1000000,
        .tx = {  0xbe98, /* tx cfg0 */
                  0x8800, /* tx cfg1 */
                  0x0000, /* tx cfg2 */
@@ -1990,7 +1990,7 @@ static const struct intel_c20pll_state mtl_c20_hdmi_1000 
= {
 };
 
 static const struct intel_c20pll_state mtl_c20_hdmi_1200 = {
-       .clock = 12000000,
+       .clock = 1200000,
        .tx = {  0xbe98, /* tx cfg0 */
                  0x8800, /* tx cfg1 */
                  0x0000, /* tx cfg2 */
-- 
2.34.1