On Fri, Jan 30, 2026 at 02:43:56AM +0530, Uma Shankar wrote: > Make intel_display_power_well.c free from including i915_reg.h. > > v2: Include specific pcode header, drop common header (Jani) > > Signed-off-by: Uma Shankar <[email protected]> > --- > drivers/gpu/drm/i915/display/intel_display_power_well.c | 2 +- > drivers/gpu/drm/i915/display/intel_display_regs.h | 2 ++ > drivers/gpu/drm/i915/i915_reg.h | 3 --- > 3 files changed, 3 insertions(+), 4 deletions(-) > > diff --git a/drivers/gpu/drm/i915/display/intel_display_power_well.c > b/drivers/gpu/drm/i915/display/intel_display_power_well.c > index 6f9bc6f9615e..f98de1baa63d 100644 > --- a/drivers/gpu/drm/i915/display/intel_display_power_well.c > +++ b/drivers/gpu/drm/i915/display/intel_display_power_well.c > @@ -6,8 +6,8 @@ > #include <linux/iopoll.h> > > #include <drm/drm_print.h> > +#include <drm/intel/intel_pcode.h> > > -#include "i915_reg.h" > #include "intel_backlight_regs.h" > #include "intel_combo_phy.h" > #include "intel_combo_phy_regs.h" > diff --git a/drivers/gpu/drm/i915/display/intel_display_regs.h > b/drivers/gpu/drm/i915/display/intel_display_regs.h > index 4a9b7560ce8c..758749c5c322 100644 > --- a/drivers/gpu/drm/i915/display/intel_display_regs.h > +++ b/drivers/gpu/drm/i915/display/intel_display_regs.h > @@ -359,6 +359,8 @@ > #define FW_CSPWRDWNEN (1 << 15) > > #define MI_ARB_VLV _MMIO(VLV_DISPLAY_BASE + 0x6504) > +/* Disable display A/B trickle feed */ > +#define MI_ARB_DISPLAY_TRICKLE_FEED_DISABLE (1 << 2) > > #define CZCLK_CDCLK_FREQ_RATIO _MMIO(VLV_DISPLAY_BASE + 0x6508) > #define CDCLK_FREQ_SHIFT 4 > diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h > index 9cd7fce09ebe..e4fc61dcd384 100644 > --- a/drivers/gpu/drm/i915/i915_reg.h > +++ b/drivers/gpu/drm/i915/i915_reg.h > @@ -428,9 +428,6 @@ > #define MI_ARB_LOW_PRIORITY_GRACE_4KB (0 << 4) /* > default */ > #define MI_ARB_LOW_PRIORITY_GRACE_8KB (1 << 4) > > -/* Disable display A/B trickle feed */ > -#define MI_ARB_DISPLAY_TRICKLE_FEED_DISABLE (1 << 2) > -
Instead of confusing where this bit lives on most platforms (MI_ARB_STATE) we should probably just add a separate defition for the VLV bit (since it has a separate register offset definition as well). > /* Set display plane priority */ > #define MI_ARB_DISPLAY_PRIORITY_A_B (0 << 0) /* > display A > display B */ > #define MI_ARB_DISPLAY_PRIORITY_B_A (1 << 0) /* > display B > display A */ > -- > 2.50.1 -- Ville Syrjälä Intel
