On Fri, Jan 30, 2026 at 02:43:50AM +0530, Uma Shankar wrote: > Move FW_BLC_SELF to common header to make i9xx_wm.c > free from i915_reg.h include. Introduce a common > intel_gmd_misc_regs.h to define common miscellaneous > register definitions across graphics and display. > > v2: Introdue a common misc header for GMD > > Signed-off-by: Uma Shankar <[email protected]> > --- > drivers/gpu/drm/i915/display/i9xx_wm.c | 2 +- > .../gpu/drm/i915/display/intel_display_regs.h | 8 ++++++- > drivers/gpu/drm/i915/i915_reg.h | 20 +----------------- > include/drm/intel/intel_gmd_misc_regs.h | 21 +++++++++++++++++++ > 4 files changed, 30 insertions(+), 21 deletions(-) > create mode 100644 include/drm/intel/intel_gmd_misc_regs.h > > diff --git a/drivers/gpu/drm/i915/display/i9xx_wm.c > b/drivers/gpu/drm/i915/display/i9xx_wm.c > index 39dfceb438ae..24f898efa9dd 100644 > --- a/drivers/gpu/drm/i915/display/i9xx_wm.c > +++ b/drivers/gpu/drm/i915/display/i9xx_wm.c > @@ -6,8 +6,8 @@ > #include <linux/iopoll.h> > > #include <drm/drm_print.h> > +#include <drm/intel/intel_gmd_misc_regs.h> > > -#include "i915_reg.h" > #include "i9xx_wm.h" > #include "i9xx_wm_regs.h" > #include "intel_atomic.h" > diff --git a/drivers/gpu/drm/i915/display/intel_display_regs.h > b/drivers/gpu/drm/i915/display/intel_display_regs.h > index 0164dcbb709f..680020e590cb 100644 > --- a/drivers/gpu/drm/i915/display/intel_display_regs.h > +++ b/drivers/gpu/drm/i915/display/intel_display_regs.h > @@ -4,6 +4,7 @@ > #ifndef __INTEL_DISPLAY_REGS_H__ > #define __INTEL_DISPLAY_REGS_H__ > > +#include <drm/intel/intel_gmd_misc_regs.h> > #include "intel_display_reg_defs.h" > > #define GU_CNTL_PROTECTED _MMIO(0x10100C) > @@ -3119,6 +3120,11 @@ enum skl_power_gate { > #define MTL_TRAS_MASK REG_GENMASK(16, 8) > #define MTL_TRDPRE_MASK REG_GENMASK(7, 0) > > - > +#define FW_BLC _MMIO(0x20d8) > +#define FW_BLC2 _MMIO(0x20dc) > +#define FW_BLC_SELF _MMIO(0x20e0) /* 915+ only */ > +#define FW_BLC_SELF_EN_MASK REG_BIT(31) > +#define FW_BLC_SELF_FIFO_MASK REG_BIT(16) /* 945 only */ > +#define FW_BLC_SELF_EN REG_BIT(15) /* 945 only */ > > #endif /* __INTEL_DISPLAY_REGS_H__ */ > diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h > index 6cb72e6e9086..b4b749e52b5b 100644 > --- a/drivers/gpu/drm/i915/i915_reg.h > +++ b/drivers/gpu/drm/i915/i915_reg.h > @@ -26,6 +26,7 @@ > #define _I915_REG_H_ > > #include <drm/intel/intel_pcode.h> > +#include <drm/intel/intel_gmd_misc_regs.h> > #include "i915_reg_defs.h" > #include "display/intel_display_reg_defs.h" > > @@ -394,24 +395,10 @@ > > #define GEN2_ERROR_REGS I915_ERROR_REGS(EMR, EIR) > > -#define INSTPM _MMIO(0x20c0) > -#define INSTPM_SELF_EN (1 << 12) /* 915GM only */ > -#define INSTPM_AGPBUSY_INT_EN (1 << 11) /* gen3: when disabled, pending > interrupts > - will not assert AGPBUSY# and will only > - be delivered when out of C3. */ > -#define INSTPM_FORCE_ORDERING (1 << 7) /* > GEN6+ */ > -#define INSTPM_TLB_INVALIDATE (1 << 9) > -#define INSTPM_SYNC_FLUSH (1 << 5) > #define MEM_MODE _MMIO(0x20cc) > #define MEM_DISPLAY_B_TRICKLE_FEED_DISABLE (1 << 3) /* 830 only */ > #define MEM_DISPLAY_A_TRICKLE_FEED_DISABLE (1 << 2) /* 830/845 only */ > #define MEM_DISPLAY_TRICKLE_FEED_DISABLE (1 << 2) /* 85x only */ > -#define FW_BLC _MMIO(0x20d8) > -#define FW_BLC2 _MMIO(0x20dc) > -#define FW_BLC_SELF _MMIO(0x20e0) /* 915+ only */ > -#define FW_BLC_SELF_EN_MASK REG_BIT(31) > -#define FW_BLC_SELF_FIFO_MASK REG_BIT(16) /* 945 only */ > -#define FW_BLC_SELF_EN REG_BIT(15) /* 945 only */ > #define MM_BURST_LENGTH 0x00700000 > #define MM_FIFO_WATERMARK 0x0001F000 > #define LM_BURST_LENGTH 0x00000700 > @@ -834,11 +821,6 @@ > #define KVM_CONFIG_CHANGE_NOTIFICATION_SELECT REG_BIT(14) > > > -#define DISP_ARB_CTL _MMIO(0x45000) > -#define DISP_FBC_MEMORY_WAKE REG_BIT(31) > -#define DISP_TILE_SURFACE_SWIZZLING REG_BIT(13) > -#define DISP_FBC_WM_DIS REG_BIT(15) > - > #define GEN8_CHICKEN_DCPR_1 _MMIO(0x46430) > #define _LATENCY_REPORTING_REMOVED_PIPE_D REG_BIT(31) > #define SKL_SELECT_ALTERNATE_DC_EXIT REG_BIT(30) > diff --git a/include/drm/intel/intel_gmd_misc_regs.h > b/include/drm/intel/intel_gmd_misc_regs.h > new file mode 100644 > index 000000000000..377f4e383699 > --- /dev/null > +++ b/include/drm/intel/intel_gmd_misc_regs.h > @@ -0,0 +1,21 @@ > +/* SPDX-License-Identifier: MIT */ > +/* Copyright © 2026 Intel Corporation */ > + > +#ifndef _INTEL_GMD_MISC_REG_H_ > +#define _INTEL_GMD_MISC_REG_H_
What is a "GMD"? > + > +#define DISP_ARB_CTL _MMIO(0x45000) > +#define DISP_FBC_MEMORY_WAKE REG_BIT(31) > +#define DISP_TILE_SURFACE_SWIZZLING REG_BIT(13) > +#define DISP_FBC_WM_DIS REG_BIT(15) That's just a regular display register. I suspect most of the other registers relatd to the arbiter/etc. are in intel_display_regs.h > + > +#define INSTPM _MMIO(0x20c0) > +#define INSTPM_SELF_EN (1 << 12) /* 915GM only */ > +#define INSTPM_AGPBUSY_INT_EN (1 << 11) /* gen3: when disabled, pending > interrupts > + will not assert AGPBUSY# and will only > + be delivered when out of C3. */ > +#define INSTPM_FORCE_ORDERING (1 << 7) /* > GEN6+ */ > +#define INSTPM_TLB_INVALIDATE (1 << 9) > +#define INSTPM_SYNC_FLUSH (1 << 5) This is not even a display register. -- Ville Syrjälä Intel
