On Thu, 05 Feb 2026, Uma Shankar <[email protected]> wrote: > Move VLV_IRQ_REGS to common header for interrupt to make > intel_display_irq.c free from including i915_reg.h. > > v2: Move interrupt to dedicated header (Jani) > > Signed-off-by: Uma Shankar <[email protected]>
Reviewed-by: Jani Nikula <[email protected]> > --- > .../gpu/drm/i915/display/intel_display_irq.c | 1 - > .../gpu/drm/i915/display/intel_display_regs.h | 5 ++ > drivers/gpu/drm/i915/gt/intel_gt_irq.c | 2 + > drivers/gpu/drm/i915/gt/intel_rc6.c | 1 + > drivers/gpu/drm/i915/gvt/handlers.c | 1 + > drivers/gpu/drm/i915/gvt/interrupt.c | 1 + > drivers/gpu/drm/i915/i915_reg.h | 52 ------------------- > drivers/gpu/drm/i915/intel_clock_gating.c | 1 + > drivers/gpu/drm/i915/intel_gvt_mmio_table.c | 2 + > drivers/gpu/drm/i915/vlv_suspend.c | 1 + > include/drm/intel/intel_gmd_interrupt_regs.h | 49 +++++++++++++++++ > 11 files changed, 63 insertions(+), 53 deletions(-) > > diff --git a/drivers/gpu/drm/i915/display/intel_display_irq.c > b/drivers/gpu/drm/i915/display/intel_display_irq.c > index 432a9c895c39..bd0eb1f46919 100644 > --- a/drivers/gpu/drm/i915/display/intel_display_irq.c > +++ b/drivers/gpu/drm/i915/display/intel_display_irq.c > @@ -7,7 +7,6 @@ > #include <drm/drm_vblank.h> > #include <drm/intel/intel_gmd_interrupt_regs.h> > > -#include "i915_reg.h" > #include "icl_dsi_regs.h" > #include "intel_crtc.h" > #include "intel_de.h" > diff --git a/drivers/gpu/drm/i915/display/intel_display_regs.h > b/drivers/gpu/drm/i915/display/intel_display_regs.h > index dcb8cab7b30b..1c77a7de2d6e 100644 > --- a/drivers/gpu/drm/i915/display/intel_display_regs.h > +++ b/drivers/gpu/drm/i915/display/intel_display_regs.h > @@ -1470,6 +1470,11 @@ > #define DE_PIPEA_FIFO_UNDERRUN (1 << 0) > #define DE_PIPE_FIFO_UNDERRUN(pipe) (1 << (8 * (pipe))) > > +/* Display Internal Timeout Register */ > +#define RM_TIMEOUT _MMIO(0x42060) > +#define RM_TIMEOUT_REG_CAPTURE _MMIO(0x420E0) > +#define MMIO_TIMEOUT_US(us) ((us) << 0) > + > #define GEN8_DE_MISC_ISR _MMIO(0x44460) > #define GEN8_DE_MISC_IMR _MMIO(0x44464) > #define GEN8_DE_MISC_IIR _MMIO(0x44468) > diff --git a/drivers/gpu/drm/i915/gt/intel_gt_irq.c > b/drivers/gpu/drm/i915/gt/intel_gt_irq.c > index 75e802e10be2..d85c849c0081 100644 > --- a/drivers/gpu/drm/i915/gt/intel_gt_irq.c > +++ b/drivers/gpu/drm/i915/gt/intel_gt_irq.c > @@ -5,6 +5,8 @@ > > #include <linux/sched/clock.h> > > +#include <drm/intel/intel_gmd_interrupt_regs.h> > + > #include "i915_drv.h" > #include "i915_irq.h" > #include "i915_reg.h" > diff --git a/drivers/gpu/drm/i915/gt/intel_rc6.c > b/drivers/gpu/drm/i915/gt/intel_rc6.c > index 942ac1ebecee..5c316f734c4a 100644 > --- a/drivers/gpu/drm/i915/gt/intel_rc6.c > +++ b/drivers/gpu/drm/i915/gt/intel_rc6.c > @@ -8,6 +8,7 @@ > > #include <drm/drm_print.h> > #include <drm/intel/intel_pcode_regs.h> > +#include <drm/intel/intel_gmd_interrupt_regs.h> > > #include "display/vlv_clock.h" > #include "gem/i915_gem_region.h" > diff --git a/drivers/gpu/drm/i915/gvt/handlers.c > b/drivers/gpu/drm/i915/gvt/handlers.c > index 2e9d9d0638ae..4f65ced906da 100644 > --- a/drivers/gpu/drm/i915/gvt/handlers.c > +++ b/drivers/gpu/drm/i915/gvt/handlers.c > @@ -41,6 +41,7 @@ > #include <drm/display/drm_dp.h> > #include <drm/drm_print.h> > #include <drm/intel/intel_pcode_regs.h> > +#include <drm/intel/intel_gmd_interrupt_regs.h> > > #include "display/bxt_dpio_phy_regs.h" > #include "display/i9xx_plane_regs.h" > diff --git a/drivers/gpu/drm/i915/gvt/interrupt.c > b/drivers/gpu/drm/i915/gvt/interrupt.c > index 91d22b1c62e2..f85113218037 100644 > --- a/drivers/gpu/drm/i915/gvt/interrupt.c > +++ b/drivers/gpu/drm/i915/gvt/interrupt.c > @@ -32,6 +32,7 @@ > #include <linux/eventfd.h> > > #include <drm/drm_print.h> > +#include <drm/intel/intel_gmd_interrupt_regs.h> > > #include "display/intel_display_regs.h" > > diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h > index 5cb53a8c451a..7f3d5b7f7abd 100644 > --- a/drivers/gpu/drm/i915/i915_reg.h > +++ b/drivers/gpu/drm/i915/i915_reg.h > @@ -335,9 +335,6 @@ > > #define VLV_GU_CTL0 _MMIO(VLV_DISPLAY_BASE + 0x2030) > #define VLV_GU_CTL1 _MMIO(VLV_DISPLAY_BASE + 0x2034) > -#define SCPD0 _MMIO(0x209c) /* 915+ only */ > -#define SCPD_FBC_IGNORE_3D (1 << 6) > -#define CSTATE_RENDER_CLOCK_GATE_DISABLE (1 << 5) > #define GEN2_IER _MMIO(0x20a0) > #define GEN2_IIR _MMIO(0x20a4) > #define GEN2_IMR _MMIO(0x20a8) > @@ -350,13 +347,6 @@ > #define GINT_DIS (1 << 22) > #define GCFG_DIS (1 << 8) > #define VLV_GUNIT_CLOCK_GATE2 _MMIO(VLV_DISPLAY_BASE + 0x2064) > -#define VLV_IIR_RW _MMIO(VLV_DISPLAY_BASE + 0x2084) > -#define VLV_IER _MMIO(VLV_DISPLAY_BASE + 0x20a0) > -#define VLV_IIR _MMIO(VLV_DISPLAY_BASE + 0x20a4) > -#define VLV_IMR _MMIO(VLV_DISPLAY_BASE + 0x20a8) > -#define VLV_ISR _MMIO(VLV_DISPLAY_BASE + 0x20ac) > -#define VLV_PCBR _MMIO(VLV_DISPLAY_BASE + 0x2120) > -#define VLV_PCBR_ADDR_SHIFT 12 > > #define EIR _MMIO(0x20b0) > #define EMR _MMIO(0x20b4) > @@ -682,11 +672,6 @@ > #define PCH_3DCGDIS1 _MMIO(0x46024) > # define VFMUNIT_CLOCK_GATE_DISABLE (1 << 11) > > -/* Display Internal Timeout Register */ > -#define RM_TIMEOUT _MMIO(0x42060) > -#define RM_TIMEOUT_REG_CAPTURE _MMIO(0x420E0) > -#define MMIO_TIMEOUT_US(us) ((us) << 0) > - > #define VLV_MASTER_IER _MMIO(0x4400c) /* Gunit master > IER */ > #define MASTER_INTERRUPT_ENABLE (1 << 31) > > @@ -699,24 +684,6 @@ > GTIER, \ > GTIIR) > > -#define GEN8_MASTER_IRQ _MMIO(0x44200) > -#define GEN8_MASTER_IRQ_CONTROL (1 << 31) > -#define GEN8_PCU_IRQ (1 << 30) > -#define GEN8_DE_PCH_IRQ (1 << 23) > -#define GEN8_DE_MISC_IRQ (1 << 22) > -#define GEN8_DE_PORT_IRQ (1 << 20) > -#define GEN8_DE_PIPE_C_IRQ (1 << 18) > -#define GEN8_DE_PIPE_B_IRQ (1 << 17) > -#define GEN8_DE_PIPE_A_IRQ (1 << 16) > -#define GEN8_DE_PIPE_IRQ(pipe) (1 << (16 + (pipe))) > -#define GEN8_GT_VECS_IRQ (1 << 6) > -#define GEN8_GT_GUC_IRQ (1 << 5) > -#define GEN8_GT_PM_IRQ (1 << 4) > -#define GEN8_GT_VCS1_IRQ (1 << 3) /* NB: VCS2 in bspec! */ > -#define GEN8_GT_VCS0_IRQ (1 << 2) /* NB: VCS1 in bpsec! */ > -#define GEN8_GT_BCS_IRQ (1 << 1) > -#define GEN8_GT_RCS_IRQ (1 << 0) > - > #define GEN8_GT_ISR(which) _MMIO(0x44300 + (0x10 * (which))) > #define GEN8_GT_IMR(which) _MMIO(0x44304 + (0x10 * (which))) > #define GEN8_GT_IIR(which) _MMIO(0x44308 + (0x10 * (which))) > @@ -742,25 +709,6 @@ > GEN8_PCU_IER, \ > GEN8_PCU_IIR) > > -#define GEN11_GU_MISC_ISR _MMIO(0x444f0) > -#define GEN11_GU_MISC_IMR _MMIO(0x444f4) > -#define GEN11_GU_MISC_IIR _MMIO(0x444f8) > -#define GEN11_GU_MISC_IER _MMIO(0x444fc) > -#define GEN11_GU_MISC_GSE (1 << 27) > - > -#define GEN11_GU_MISC_IRQ_REGS > I915_IRQ_REGS(GEN11_GU_MISC_IMR, \ > - GEN11_GU_MISC_IER, \ > - GEN11_GU_MISC_IIR) > - > -#define GEN11_GFX_MSTR_IRQ _MMIO(0x190010) > -#define GEN11_MASTER_IRQ (1 << 31) > -#define GEN11_PCU_IRQ (1 << 30) > -#define GEN11_GU_MISC_IRQ (1 << 29) > -#define GEN11_DISPLAY_IRQ (1 << 16) > -#define GEN11_GT_DW_IRQ(x) (1 << (x)) > -#define GEN11_GT_DW1_IRQ (1 << 1) > -#define GEN11_GT_DW0_IRQ (1 << 0) > - > #define DG1_MSTR_TILE_INTR _MMIO(0x190008) > #define DG1_MSTR_IRQ REG_BIT(31) > #define DG1_MSTR_TILE(t) REG_BIT(t) > diff --git a/drivers/gpu/drm/i915/intel_clock_gating.c > b/drivers/gpu/drm/i915/intel_clock_gating.c > index 1ad31435bd3f..d0400ea2ffc7 100644 > --- a/drivers/gpu/drm/i915/intel_clock_gating.c > +++ b/drivers/gpu/drm/i915/intel_clock_gating.c > @@ -27,6 +27,7 @@ > > #include <drm/drm_print.h> > #include <drm/intel/intel_gmd_misc_regs.h> > +#include <drm/intel/intel_gmd_interrupt_regs.h> > > #include "display/i9xx_plane_regs.h" > #include "display/intel_display.h" > diff --git a/drivers/gpu/drm/i915/intel_gvt_mmio_table.c > b/drivers/gpu/drm/i915/intel_gvt_mmio_table.c > index c8a51e773086..ae42818ab6e0 100644 > --- a/drivers/gpu/drm/i915/intel_gvt_mmio_table.c > +++ b/drivers/gpu/drm/i915/intel_gvt_mmio_table.c > @@ -6,6 +6,8 @@ > #include <drm/intel/intel_pcode_regs.h> > #include <drm/intel/intel_gmd_misc_regs.h> > > +#include <drm/intel/intel_gmd_interrupt_regs.h> > + > #include "display/bxt_dpio_phy_regs.h" > #include "display/i9xx_plane_regs.h" > #include "display/i9xx_wm_regs.h" > diff --git a/drivers/gpu/drm/i915/vlv_suspend.c > b/drivers/gpu/drm/i915/vlv_suspend.c > index bace7b38329b..1e4343fe5574 100644 > --- a/drivers/gpu/drm/i915/vlv_suspend.c > +++ b/drivers/gpu/drm/i915/vlv_suspend.c > @@ -7,6 +7,7 @@ > #include <linux/kernel.h> > > #include <drm/drm_print.h> > +#include <drm/intel/intel_gmd_interrupt_regs.h> > > #include "gt/intel_gt_regs.h" > > diff --git a/include/drm/intel/intel_gmd_interrupt_regs.h > b/include/drm/intel/intel_gmd_interrupt_regs.h > index dc9d5fc29ff6..ce66c4151e76 100644 > --- a/include/drm/intel/intel_gmd_interrupt_regs.h > +++ b/include/drm/intel/intel_gmd_interrupt_regs.h > @@ -40,4 +40,53 @@ > #define I915_ASLE_INTERRUPT (1 << 0) > #define I915_BSD_USER_INTERRUPT (1 << 25) > > +#define GEN8_MASTER_IRQ _MMIO(0x44200) > +#define GEN8_MASTER_IRQ_CONTROL (1 << 31) > +#define GEN8_PCU_IRQ (1 << 30) > +#define GEN8_DE_PCH_IRQ (1 << 23) > +#define GEN8_DE_MISC_IRQ (1 << 22) > +#define GEN8_DE_PORT_IRQ (1 << 20) > +#define GEN8_DE_PIPE_C_IRQ (1 << 18) > +#define GEN8_DE_PIPE_B_IRQ (1 << 17) > +#define GEN8_DE_PIPE_A_IRQ (1 << 16) > +#define GEN8_DE_PIPE_IRQ(pipe) (1 << (16 + (pipe))) > +#define GEN8_GT_VECS_IRQ (1 << 6) > +#define GEN8_GT_GUC_IRQ (1 << 5) > +#define GEN8_GT_PM_IRQ (1 << 4) > +#define GEN8_GT_VCS1_IRQ (1 << 3) /* NB: VCS2 in bspec! */ > +#define GEN8_GT_VCS0_IRQ (1 << 2) /* NB: VCS1 in bpsec! */ > +#define GEN8_GT_BCS_IRQ (1 << 1) > +#define GEN8_GT_RCS_IRQ (1 << 0) > + > +#define GEN11_GU_MISC_ISR _MMIO(0x444f0) > +#define GEN11_GU_MISC_IMR _MMIO(0x444f4) > +#define GEN11_GU_MISC_IIR _MMIO(0x444f8) > +#define GEN11_GU_MISC_IER _MMIO(0x444fc) > +#define GEN11_GU_MISC_GSE (1 << 27) > + > +#define GEN11_GU_MISC_IRQ_REGS > I915_IRQ_REGS(GEN11_GU_MISC_IMR, \ > + GEN11_GU_MISC_IER, \ > + GEN11_GU_MISC_IIR) > + > +#define GEN11_GFX_MSTR_IRQ _MMIO(0x190010) > +#define GEN11_MASTER_IRQ (1 << 31) > +#define GEN11_PCU_IRQ (1 << 30) > +#define GEN11_GU_MISC_IRQ (1 << 29) > +#define GEN11_DISPLAY_IRQ (1 << 16) > +#define GEN11_GT_DW_IRQ(x) (1 << (x)) > +#define GEN11_GT_DW1_IRQ (1 << 1) > +#define GEN11_GT_DW0_IRQ (1 << 0) > + > +#define SCPD0 _MMIO(0x209c) /* 915+ only */ > +#define SCPD_FBC_IGNORE_3D (1 << 6) > +#define CSTATE_RENDER_CLOCK_GATE_DISABLE (1 << 5) > + > +#define VLV_IIR_RW _MMIO(VLV_DISPLAY_BASE + 0x2084) > +#define VLV_IER _MMIO(VLV_DISPLAY_BASE + 0x20a0) > +#define VLV_IIR _MMIO(VLV_DISPLAY_BASE + 0x20a4) > +#define VLV_IMR _MMIO(VLV_DISPLAY_BASE + 0x20a8) > +#define VLV_ISR _MMIO(VLV_DISPLAY_BASE + 0x20ac) > +#define VLV_PCBR _MMIO(VLV_DISPLAY_BASE + 0x2120) > +#define VLV_PCBR_ADDR_SHIFT 12 > + > #endif -- Jani Nikula, Intel
