Common mode timing generator (CMTG) support is added NVL onwards. Enable CMTG which will be needed by other fearure like dynamic dc state enablement later.
Testing ongoing, currently counters are incrementing as expected. Animesh Manna (13): drm/i915/cmtg: Add intel_cmtg_is_allowed() for CMTG drm/i915/cmtg: Set CMTG clock select drm/i915/cmtg: Add cmtg transcoder offset in struct _device_info drm/i915/cmtg: Set timings for CMTG drm/i915/cmtg: Program VRR registers of CMTG drm/i915/cmtg: Set transcoder mn for CMTG drm/i915/cmtg: Add hook to enable CMTG with sync to port drm/i915/cmtg: Add a hook to make eDP transcoder secondary drm/i915/cmtg: Split CMTG support check from intel_cmtg_is_allowed() drm/i915/cmtg: Add CMTG interrupt handling drm/i915/cmtg: Add trigger to enable/disable cmtg drm/i915/cmtg: Restore CMTG after DC6 entry [NOT FOR REVIEW] debug patch Dibin Moolakadan Subrahmanian (3): drm/i915/cmtg: Modify existing hook to disable CMTG drm/i915/cmtg: Add CMTG HWGB programming drm/i915/cmtg: Add CMTG scan line programming drivers/gpu/drm/i915/display/intel_cmtg.c | 328 +++++++++++++++++- drivers/gpu/drm/i915/display/intel_cmtg.h | 15 + .../gpu/drm/i915/display/intel_cmtg_regs.h | 24 +- drivers/gpu/drm/i915/display/intel_cx0_phy.c | 5 + drivers/gpu/drm/i915/display/intel_display.c | 35 ++ .../drm/i915/display/intel_display_device.c | 14 + .../drm/i915/display/intel_display_device.h | 2 +- .../gpu/drm/i915/display/intel_display_irq.c | 12 + .../drm/i915/display/intel_display_limits.h | 2 + .../drm/i915/display/intel_display_power.c | 25 ++ .../drm/i915/display/intel_display_power.h | 3 + .../gpu/drm/i915/display/intel_display_regs.h | 6 + .../drm/i915/display/intel_display_types.h | 4 + drivers/gpu/drm/i915/display/intel_vrr.c | 5 + 14 files changed, 469 insertions(+), 11 deletions(-) -- 2.29.0
