Now that intel_sa_info contains bandwidth parameters specific to the
display IP, we can drop many duplicates and reuse from previous
releases.
Let's do that and also simplify intel_bw_init_hw() while at it.
v2:
- Drop rkl_sa_info and reuse icl_sa_info. (Matt)
- Add comment explaining RKL's display's peculiarity on using ICL's
parameters. (Matt)
- Don't rename xelpdp_sa_info to mtl_sa_info. Renaming of instances
to use IP names will be done in upcoming changes.
Reviewed-by: Matt Roper <[email protected]>
Signed-off-by: Gustavo Sousa <[email protected]>
---
drivers/gpu/drm/i915/display/intel_bw.c | 51 ++++++++-------------------------
1 file changed, 12 insertions(+), 39 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_bw.c
b/drivers/gpu/drm/i915/display/intel_bw.c
index 351ecf741b54..a956b09028f3 100644
--- a/drivers/gpu/drm/i915/display/intel_bw.c
+++ b/drivers/gpu/drm/i915/display/intel_bw.c
@@ -477,36 +477,11 @@ static const struct intel_sa_info tgl_sa_info = {
.displayrtids = 256,
};
-static const struct intel_sa_info rkl_sa_info = {
- .deburst = 8,
- .displayrtids = 128,
-};
-
-static const struct intel_sa_info adls_sa_info = {
- .deburst = 16,
- .displayrtids = 256,
-};
-
-static const struct intel_sa_info adlp_sa_info = {
- .deburst = 16,
- .displayrtids = 256,
-};
-
static const struct intel_sa_info mtl_sa_info = {
.deburst = 32,
.displayrtids = 256,
};
-static const struct intel_sa_info xe3lpd_sa_info = {
- .deburst = 32,
- .displayrtids = 256,
-};
-
-static const struct intel_sa_info xe3lpd_3002_sa_info = {
- .deburst = 32,
- .displayrtids = 256,
-};
-
static int icl_get_bw_info(struct intel_display *display,
const struct dram_info *dram_info,
const struct intel_soc_bw_params *soc_bw_params,
@@ -876,25 +851,23 @@ void intel_bw_init_hw(struct intel_display *display)
if (DISPLAY_VER(display) >= 35)
drm_WARN_ON(display->drm, dram_info->ecc_impacting_de_bw);
- if (DISPLAY_VER(display) >= 30) {
- if (DISPLAY_VERx100(display) == 3002)
- tgl_get_bw_info(display, dram_info, soc_bw_params,
&xe3lpd_3002_sa_info);
- else
- tgl_get_bw_info(display, dram_info, soc_bw_params,
&xe3lpd_sa_info);
- } else if (DISPLAY_VERx100(display) >= 1401 && display->platform.dgfx) {
+ if (DISPLAY_VERx100(display) >= 1401 && display->platform.dgfx) {
xe2_hpd_get_bw_info(display, dram_info, soc_bw_params);
} else if (DISPLAY_VER(display) >= 14) {
tgl_get_bw_info(display, dram_info, soc_bw_params,
&mtl_sa_info);
} else if (display->platform.dg2) {
dg2_get_bw_info(display);
- } else if (display->platform.alderlake_p) {
- tgl_get_bw_info(display, dram_info, soc_bw_params,
&adlp_sa_info);
- } else if (display->platform.alderlake_s) {
- tgl_get_bw_info(display, dram_info, soc_bw_params,
&adls_sa_info);
- } else if (display->platform.rocketlake) {
- tgl_get_bw_info(display, dram_info, soc_bw_params,
&rkl_sa_info);
- } else if (DISPLAY_VER(display) == 12) {
- tgl_get_bw_info(display, dram_info, soc_bw_params,
&tgl_sa_info);
+ } else if (DISPLAY_VER(display) >= 12) {
+ /*
+ * RKL's SoC was based on ICL and the display, even though being
+ * gen12, had changes to the memory interface to match gen11's,
+ * consequently inheriting gen11's display-specific bandwidth
+ * parameters.
+ */
+ if (display->platform.rocketlake)
+ tgl_get_bw_info(display, dram_info, soc_bw_params,
&icl_sa_info);
+ else
+ tgl_get_bw_info(display, dram_info, soc_bw_params,
&tgl_sa_info);
} else if (DISPLAY_VER(display) == 11) {
icl_get_bw_info(display, dram_info, soc_bw_params,
&icl_sa_info);
}
--
2.53.0
