Just like it is done for the platform-specific bandwidth parameters, use
a separate function named get_display_bw_params() to return the display
IP-specific parameters. This simplifies intel_bw_init_hw() by having
just one call for each of the *_get_bw_info() functions.
v2:
- Prefer to call get_display_bw_params() only once in
intel_bw_init_hw() instead of having multiple calls in each of the
affected *_get_bw_info() functions. (Jani)
v3:
- Call get_display_bw_params() only after the check on
HAS_DISPLAY(display). (Jani)
- Return &gen11_bw_params only if display version is 11. (Matt)
Cc: Jani Nikula <[email protected]>
Cc: Matt Roper <[email protected]>
Signed-off-by: Gustavo Sousa <[email protected]>
---
drivers/gpu/drm/i915/display/intel_bw.c | 41 ++++++++++++++++++++++-----------
1 file changed, 28 insertions(+), 13 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_bw.c
b/drivers/gpu/drm/i915/display/intel_bw.c
index 5821397dc27f..07407384e261 100644
--- a/drivers/gpu/drm/i915/display/intel_bw.c
+++ b/drivers/gpu/drm/i915/display/intel_bw.c
@@ -490,6 +490,30 @@ static const struct intel_display_bw_params
xelpdp_bw_params = {
.displayrtids = 256,
};
+static const struct intel_display_bw_params *get_display_bw_params(struct
intel_display *display)
+{
+ if (DISPLAY_VER(display) >= 14) {
+ return &xelpdp_bw_params;
+ } else if (DISPLAY_VER(display) >= 12) {
+ /*
+ * RKL's SoC was based on ICL and the display, even though being
+ * gen12, had changes to the memory interface to match gen11's,
+ * consequently inheriting gen11's display-specific bandwidth
+ * parameters.
+ */
+ if (display->platform.rocketlake)
+ return &gen11_bw_params;
+ else
+ return &gen12_bw_params;
+ } else if (DISPLAY_VER(display) == 11) {
+ return &gen11_bw_params;
+ }
+
+ drm_WARN(display->drm, 1, "Display-specific bandwidth parameters not
found!\n");
+
+ return NULL;
+}
+
static int icl_get_bw_info(struct intel_display *display,
const struct dram_info *dram_info,
const struct intel_soc_bw_params *soc_bw_params,
@@ -840,6 +864,7 @@ void intel_bw_init_hw(struct intel_display *display)
{
const struct dram_info *dram_info;
const struct intel_soc_bw_params *soc_bw_params;
+ const struct intel_display_bw_params *display_bw_params;
if (!HAS_DISPLAY(display))
return;
@@ -849,6 +874,7 @@ void intel_bw_init_hw(struct intel_display *display)
dram_info = intel_dram_info(display);
soc_bw_params = get_soc_bw_params(display);
+ display_bw_params = get_display_bw_params(display);
/*
* Starting with Xe3p_LPD, the hardware tells us whether memory has ECC
@@ -861,23 +887,12 @@ void intel_bw_init_hw(struct intel_display *display)
if (DISPLAY_VERx100(display) >= 1401 && display->platform.dgfx) {
xe2_hpd_get_bw_info(display, dram_info, soc_bw_params);
- } else if (DISPLAY_VER(display) >= 14) {
- tgl_get_bw_info(display, dram_info, soc_bw_params,
&xelpdp_bw_params);
} else if (display->platform.dg2) {
dg2_get_bw_info(display);
} else if (DISPLAY_VER(display) >= 12) {
- /*
- * RKL's SoC was based on ICL and the display, even though being
- * gen12, had changes to the memory interface to match gen11's,
- * consequently inheriting gen11's display-specific bandwidth
- * parameters.
- */
- if (display->platform.rocketlake)
- tgl_get_bw_info(display, dram_info, soc_bw_params,
&gen11_bw_params);
- else
- tgl_get_bw_info(display, dram_info, soc_bw_params,
&gen12_bw_params);
+ tgl_get_bw_info(display, dram_info, soc_bw_params,
display_bw_params);
} else if (DISPLAY_VER(display) == 11) {
- icl_get_bw_info(display, dram_info, soc_bw_params,
&gen11_bw_params);
+ icl_get_bw_info(display, dram_info, soc_bw_params,
display_bw_params);
}
}
--
2.53.0
