This patch set implements two workarounds:
1. There are problem in PSR2 SDP on Prior Scanline implementation in
several panels due to eDP1.4b spec ambiguity. Two tackle this there is
Intel specific DPCD register for panel to indicate implementation
compatibility with Intel source implementation. eDP1.5 doesn't have
this problem.
2. In NVL there is an HW optimization done. When there is an SU triggered in
Capture state, Link will be kept ON post Capture CRC SDP. Before valid SU
pixels Intel source will transmit dummy pixels. Some TCONS are improperly
considering these dummy pixels as a valid pixel data. Prior NVL link was
was turned of even if there was SU triggered in Capture state and no dummy
pixels were transmitted. These dummy pixels are problem only if SDP on
prior scanline is used and Early Transport is not in use. The workaround is
to start SU area always at scanline 0.
v2:
- add INTEL_DPCD_ prefix to definitions
- use intel_display_wa
Jouni Högander (4):
drm/i915/psr: Add defininitions for INTEL_WA_REGISTER_CAPS DPCD
register
drm/i915/psr: Read Intel DPCD workaround register
drm/i915/psr: Apply Intel DPCD workaround when SDP on prior line used
drm/i915/psr: Apply SDP on prior scanline workaround for Xe3p
.../drm/i915/display/intel_display_types.h | 1 +
.../gpu/drm/i915/display/intel_display_wa.c | 2 +
.../gpu/drm/i915/display/intel_display_wa.h | 1 +
drivers/gpu/drm/i915/display/intel_dpcd.h | 15 ++++++
drivers/gpu/drm/i915/display/intel_psr.c | 49 +++++++++++++++++--
5 files changed, 63 insertions(+), 5 deletions(-)
create mode 100644 drivers/gpu/drm/i915/display/intel_dpcd.h
--
2.43.0
