On Fri, 2026-05-15 at 13:06 +0530, Ankit Nautiyal wrote: > For Legacy timing generator, if there are no panel replay/sel_update > or other > SRD constraints, the Set context latency (SCL) window should be at > least 1. > > However, for VRR timing generator the SCL window can be 0. It has > other > guardband constraints, but that are checked during guardband > computation. > > Allow SCL to be 0 for platforms that have VRR TG always on. > > Signed-off-by: Ankit Nautiyal <[email protected]>
Reviewed-by: Jouni Högander <[email protected]> > --- > drivers/gpu/drm/i915/display/intel_psr.c | 3 ++- > 1 file changed, 2 insertions(+), 1 deletion(-) > > diff --git a/drivers/gpu/drm/i915/display/intel_psr.c > b/drivers/gpu/drm/i915/display/intel_psr.c > index 5bf1d782188c..12c2e2a70bd8 100644 > --- a/drivers/gpu/drm/i915/display/intel_psr.c > +++ b/drivers/gpu/drm/i915/display/intel_psr.c > @@ -1477,7 +1477,8 @@ int _intel_psr_min_set_context_latency(const > struct intel_crtc_state *crtc_state > * SRD_STATUS is used by PSR1 and Panel Replay DP on > LunarLake. > */ > > - if (needs_sel_update || > + if (intel_vrr_always_use_vrr_tg(display) || > + needs_sel_update || > (DISPLAY_VER(display) >= 30 && needs_panel_replay) || > (DISPLAY_VER(display) < 30 && > intel_crtc_has_type(crtc_state, INTEL_OUTPUT_EDP))) > return 0;
