On Mon, 2026-05-18 at 14:24 +0300, Imre Deak wrote: > Cache the maximum common lane count together with the common link > rates. > > This is safe because the cached value is updated: > - during driver probe, before the connector is registered and can be > used for mode validation or modesetting > - during resume, before output HW state readout can query it > - during connector detection, right after updating the sink/link > capabilities > > Caching the value allows detecting max common lane count changes in > a follow-up change and keeps the tracking of max common lane count > aligned with that of common rates. > > Signed-off-by: Imre Deak <[email protected]>
Reviewed-by: Jouni Högander <[email protected]> > --- > drivers/gpu/drm/i915/display/intel_display_types.h | 1 + > drivers/gpu/drm/i915/display/intel_dp.c | 10 ++++++++-- > 2 files changed, 9 insertions(+), 2 deletions(-) > > diff --git a/drivers/gpu/drm/i915/display/intel_display_types.h > b/drivers/gpu/drm/i915/display/intel_display_types.h > index f44be5c689aef..c3811242310c8 100644 > --- a/drivers/gpu/drm/i915/display/intel_display_types.h > +++ b/drivers/gpu/drm/i915/display/intel_display_types.h > @@ -1820,6 +1820,7 @@ struct intel_dp { > /* intersection of source and sink rates */ > int num_common_rates; > int common_rates[DP_MAX_SUPPORTED_RATES]; > + int max_common_lane_count; > struct { > /* TODO: move the rest of link specific fields to > here */ > bool active; > diff --git a/drivers/gpu/drm/i915/display/intel_dp.c > b/drivers/gpu/drm/i915/display/intel_dp.c > index 06bf1fb23faff..6c4dadfc35806 100644 > --- a/drivers/gpu/drm/i915/display/intel_dp.c > +++ b/drivers/gpu/drm/i915/display/intel_dp.c > @@ -363,7 +363,7 @@ int intel_dp_max_source_lane_count(struct > intel_digital_port *dig_port) > } > > /* Theoretical max between source and sink */ > -int intel_dp_max_common_lane_count(struct intel_dp *intel_dp) > +static void intel_dp_set_max_common_lane_count(struct intel_dp > *intel_dp) > { > struct intel_digital_port *dig_port = > dp_to_dig_port(intel_dp); > int source_max = intel_dp_max_source_lane_count(dig_port); > @@ -374,7 +374,12 @@ int intel_dp_max_common_lane_count(struct > intel_dp *intel_dp) > if (lttpr_max) > sink_max = min(sink_max, lttpr_max); > > - return min3(source_max, sink_max, lane_max); > + intel_dp->max_common_lane_count = min3(source_max, sink_max, > lane_max); > +} > + > +int intel_dp_max_common_lane_count(struct intel_dp *intel_dp) > +{ > + return intel_dp->max_common_lane_count; > } > > static int forced_lane_count(struct intel_dp *intel_dp) > @@ -810,6 +815,7 @@ static void intel_dp_set_common_rates(struct > intel_dp *intel_dp) > static void intel_dp_set_common_link_params(struct intel_dp > *intel_dp) > { > intel_dp_set_common_rates(intel_dp); > + intel_dp_set_max_common_lane_count(intel_dp); > intel_dp_link_config_init(intel_dp); > } >
