> -----Original Message-----
> From: Ville Syrjälä <[email protected]>
> Sent: Friday, May 29, 2026 4:22 PM
> To: Manna, Animesh <[email protected]>
> Cc: [email protected]; [email protected]; Shankar,
> Uma <[email protected]>; Dibin Moolakadan Subrahmanian
> <[email protected]>; Nikula, Jani
> <[email protected]>
> Subject: Re: [PATCH v7 08/15] drm/i915/cmtg: Add a hook to make eDP
> transcoder secondary
>
> On Tue, May 26, 2026 at 07:08:04PM +0530, Animesh Manna wrote:
> > Program DDI_FUNC_CTL2 to configure the eDP transcoder as secondary to
> > the CMTG transcoder.
> >
> > v2:
> > - Update commit header to be more clear. [Uma]
> >
> > Reviewed-by: Uma Shankar <[email protected]>
> > Signed-off-by: Animesh Manna <[email protected]>
> > ---
> > drivers/gpu/drm/i915/display/intel_cmtg.c | 13 +++++++++++++
> > drivers/gpu/drm/i915/display/intel_cmtg.h | 1 +
> > 2 files changed, 14 insertions(+)
> >
> > diff --git a/drivers/gpu/drm/i915/display/intel_cmtg.c
> > b/drivers/gpu/drm/i915/display/intel_cmtg.c
> > index 63e430f7e63b..34715280d65d 100644
> > --- a/drivers/gpu/drm/i915/display/intel_cmtg.c
> > +++ b/drivers/gpu/drm/i915/display/intel_cmtg.c
> > @@ -359,3 +359,16 @@ void intel_cmtg_enable_sync(const struct
> intel_crtc_state *crtc_state)
> > transcoder_name(cpu_transcoder));
> > }
> > }
> > +
> > +void intel_cmtg_enable_ddi(const struct intel_crtc_state *crtc_state)
> > +{
> > + struct intel_display *display = to_intel_display(crtc_state);
> > + enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;
> > +
> > + if (!intel_cmtg_is_allowed(crtc_state))
> > + return;
> > +
> > + intel_de_rmw(display, TRANS_DDI_FUNC_CTL2(display,
> cpu_transcoder),
> > +0, CMTG_SECONDARY_MODE);
>
> We already have a place where we configure TRANS_DDI_FUNC_CTL2.
> Why is this not there?
The idea here to enable primary eDP transcoder first and then enable CMTG.
Later make eDP transcoder secondary to CMTG.
So not added in intel_ddi_enable().
Regards,
Animesh
>
> > +
> > + drm_dbg_kms(display->drm, "CMTG: %s enabled\n",
> > +transcoder_name(cpu_transcoder)); }
> > diff --git a/drivers/gpu/drm/i915/display/intel_cmtg.h
> > b/drivers/gpu/drm/i915/display/intel_cmtg.h
> > index 64ff6a19948a..12abbafa7d08 100644
> > --- a/drivers/gpu/drm/i915/display/intel_cmtg.h
> > +++ b/drivers/gpu/drm/i915/display/intel_cmtg.h
> > @@ -11,6 +11,7 @@
> > struct intel_display;
> > struct intel_crtc_state;
> >
> > +void intel_cmtg_enable_ddi(const struct intel_crtc_state
> > +*crtc_state);
> > void intel_cmtg_enable_sync(const struct intel_crtc_state
> > *crtc_state); void intel_cmtg_set_m_n(const struct intel_crtc_state
> > *crtc_state); void intel_cmtg_set_vrr_timings(const struct
> > intel_crtc_state *crtc_state);
> > --
> > 2.29.0
>
> --
> Ville Syrjälä
> Intel
