On 5/19/2026 10:33 AM, Mitul Golani wrote:
Compute Enabling of CMRR via crtc state.
Signed-off-by: Mitul Golani <[email protected]>
---
drivers/gpu/drm/i915/display/intel_vrr.c | 1 +
1 file changed, 1 insertion(+)
diff --git a/drivers/gpu/drm/i915/display/intel_vrr.c
b/drivers/gpu/drm/i915/display/intel_vrr.c
index 975c87c4ffbb..43fb6f4aaf56 100644
--- a/drivers/gpu/drm/i915/display/intel_vrr.c
+++ b/drivers/gpu/drm/i915/display/intel_vrr.c
@@ -236,6 +236,7 @@ void intel_vrr_compute_fixed_rr_timings(struct
intel_crtc_state *crtc_state,
if (HAS_CMRR(display) && is_edp) {
/* For CMRR, vmin = vmax = flipline = Dithered Vtotal */
crtc_state->vrr.vmax = cmrr_get_vtotal(crtc_state);
+ crtc_state->vrr.cmrr.enable = true;
This should be enabled only when we actually need CMRR not just on
HAS_CMRR().
Since this is the patch that finally is supposed to enable CMRR, here
are some over-arching comments (including on code that is not included
in this series).
- CMRR is supposed to be mutually exclusive with PSR2, are we taking
care of it? Right now psr_compute_config seems to only take vrr.enable
into consideration.
- The CMRR registers are armed by TRANS_CMRR_N_HI and BSpec mandates
that it should be the last CMRR register to be written. Also, indicated
by the FIXME comment in intel_vrr_tg_enable()
/*
* FIXME this might be broken as bspec seems to imply that
* even VRR_CTL_CMRR_ENABLE is armed by TRANS_CMRR_N_HI
* when enabling CMRR (but not when disabling CMRR?).
*/
The DB programming might need a re-look.
- The target rr divider bit is always set to true in
intel_dp_compute_as_sdp(). This is wrong for non-video mode refresh rates.
- Right now the implementation is only limited to eDP, I don't see a
reason why it can't be enabled for DP as well.
A few things I didn't quite get the time to look into in more detail,
but they may be worth considering for the next revision.
- There is another TODO comment in intel_vrr_get_config() which might
need some attention
/*
* #TODO: For Both VRR and CMRR the flag I915_MODE_FLAG_VRR is set for
mode_flags.
* Since CMRR is currently disabled, set this flag for VRR for now.
* Need to keep this in mind while re-enabling CMRR.
*/
- When switching from one FAVT (Fixed Average V-Total) to another some
sinks might need ramping up to the target refresh rate instead of
directly jumping to the targer refresh rate, indicated by Bit[1:0] in
DB0 of the AsyncSync SDP. May be we have to spare some thought on that too.
- CMRR is also mutually exclusive with DC balance but I think that is
already handled.
==
Chaitanya
} else {
/* For fixed rr, vmin = vmax = flipline */
crtc_state->vrr.vmax = crtc_state->hw.adjusted_mode.crtc_vtotal;
