> -----Original Message-----
> From: Manna, Animesh <[email protected]>
> Sent: Thursday, June 4, 2026 1:24 AM
> To: [email protected]; [email protected]
> Cc: Shankar, Uma <[email protected]>; Dibin Moolakadan Subrahmanian
> <[email protected]>; [email protected];
> Nikula, Jani <[email protected]>; Manna, Animesh
> <[email protected]>
> Subject: [PATCH v8 01/20] drm/i915/cmtg: Add intel_cmtg_is_allowed() for CMTG
>
> CMTG is supported on transcoder A and transcoder B with EDP, so add a
> separate helper intel_cmtg_is_allowed() to check the prerequisites for
> enabling
> CMTG. CMTG will be enabled only in specific use cases such as PSR2, PR-
> ALPM, and LOBF, and will be used in conjunction with the DC3CO feature. DC3co
> will be enabled in a separate patch.
>
> Note: Use-case-specific checks and transcoder-port compatibility validation
> will
> be handled part of DC3co feature implementation.
>
> v2:
> - Remove separate flag for DC3co from crtc_state. [Uma, Dibin]
>
> v3:
> - Do not access power domain members directly. [Jani]
>
> v4:
> - Remove check for DC3co state now. if needed add Dc3co allow check later once
> Dc3co patches are merged. [Uma]
Looks Good to me.
Reviewed-by: Uma Shankar <[email protected]>
> Bspec: 68915
> Reviewed-by: Dibin Moolakadan Subrahmanian
> <[email protected]>
> Signed-off-by: Animesh Manna <[email protected]>
> ---
> drivers/gpu/drm/i915/display/intel_cmtg.c | 14 +++++++++++++-
> drivers/gpu/drm/i915/display/intel_cmtg.h | 4 ++++
> 2 files changed, 17 insertions(+), 1 deletion(-)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_cmtg.c
> b/drivers/gpu/drm/i915/display/intel_cmtg.c
> index e1fdc6fe9762..a279f3dcd1ec 100644
> --- a/drivers/gpu/drm/i915/display/intel_cmtg.c
> +++ b/drivers/gpu/drm/i915/display/intel_cmtg.c
> @@ -4,7 +4,6 @@
> */
>
> #include <linux/string_choices.h>
> -#include <linux/types.h>
>
> #include <drm/drm_device.h>
> #include <drm/drm_print.h>
> @@ -16,6 +15,7 @@
> #include "intel_display_device.h"
> #include "intel_display_power.h"
> #include "intel_display_regs.h"
> +#include "intel_display_types.h"
>
> /**
> * DOC: Common Primary Timing Generator (CMTG) @@ -185,3 +185,15 @@
> void intel_cmtg_sanitize(struct intel_display *display)
>
> intel_cmtg_disable(display, &cmtg_config); }
> +
> +bool intel_cmtg_is_allowed(const struct intel_crtc_state *crtc_state) {
> + struct intel_display *display = to_intel_display(crtc_state);
> + enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;
> +
> + if ((cpu_transcoder == TRANSCODER_A || cpu_transcoder ==
> TRANSCODER_B) &&
> + DISPLAY_VER(display) == 35 && intel_crtc_has_type(crtc_state,
> INTEL_OUTPUT_EDP))
> + return true;
> +
> + return false;
> +}
> diff --git a/drivers/gpu/drm/i915/display/intel_cmtg.h
> b/drivers/gpu/drm/i915/display/intel_cmtg.h
> index ba62199adaa2..ed540581738f 100644
> --- a/drivers/gpu/drm/i915/display/intel_cmtg.h
> +++ b/drivers/gpu/drm/i915/display/intel_cmtg.h
> @@ -6,8 +6,12 @@
> #ifndef __INTEL_CMTG_H__
> #define __INTEL_CMTG_H__
>
> +#include <linux/types.h>
> +
> struct intel_display;
> +struct intel_crtc_state;
>
> void intel_cmtg_sanitize(struct intel_display *display);
> +bool intel_cmtg_is_allowed(const struct intel_crtc_state *crtc_state);
>
> #endif /* __INTEL_CMTG_H__ */
> --
> 2.29.0
