> -----Original Message-----
> From: Manna, Animesh <[email protected]>
> Sent: Thursday, June 4, 2026 1:24 AM
> To: [email protected]; [email protected]
> Cc: Shankar, Uma <[email protected]>; Dibin Moolakadan Subrahmanian
> <[email protected]>; [email protected];
> Nikula, Jani <[email protected]>; Manna, Animesh
> <[email protected]>
> Subject: [PATCH v8 17/20] drm/i915/cmtg: Add CMTG scan line programming
>
> From: Dibin Moolakadan Subrahmanian
> <[email protected]>
>
> Enable the hardware based guardband calculations which allows DC3co to remain
> enabled when timings are changing from one fixed refresh rate to another fixed
> refresh rate.
Looks Good to me.
Reviewed-by: Uma Shankar <[email protected]>
> Bspec: 75253
> Signed-off-by: Dibin Moolakadan Subrahmanian
> <[email protected]>
> Signed-off-by: Animesh Manna <[email protected]>
> ---
> drivers/gpu/drm/i915/display/intel_cmtg.c | 2 ++
> drivers/gpu/drm/i915/display/intel_cmtg_regs.h | 6 ++++++
> 2 files changed, 8 insertions(+)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_cmtg.c
> b/drivers/gpu/drm/i915/display/intel_cmtg.c
> index cc36784e5253..1d63b612c44b 100644
> --- a/drivers/gpu/drm/i915/display/intel_cmtg.c
> +++ b/drivers/gpu/drm/i915/display/intel_cmtg.c
> @@ -188,6 +188,7 @@ void intel_cmtg_disable(const struct intel_crtc_state
> *crtc_state)
>
> intel_de_rmw(display, TRANS_DDI_FUNC_CTL2(display,
> cpu_transcoder),
> CMTG_SECONDARY_MODE, 0);
> + intel_de_rmw(display, CMTG_SCANLINE_GB1(cpu_transcoder),
> +CMTG_HW_GB_ENABLE, 0);
>
> intel_de_rmw(display, TRANS_CMTG_CTL(cpu_transcoder),
> CMTG_ENABLE, 0);
>
> @@ -351,6 +352,7 @@ void intel_cmtg_enable_ddi(const struct intel_crtc_state
> *crtc_state)
> return;
>
> intel_de_rmw(display, TRANS_DDI_FUNC_CTL2(display,
> cpu_transcoder), 0, CMTG_SECONDARY_MODE);
> + intel_de_rmw(display, CMTG_SCANLINE_GB1(cpu_transcoder), 0,
> +CMTG_HW_GB_ENABLE);
> crtc->cmtg.enabled = true;
> drm_dbg_kms(display->drm, "CMTG: %s enabled\n",
> transcoder_name(cpu_transcoder)); } diff --git
> a/drivers/gpu/drm/i915/display/intel_cmtg_regs.h
> b/drivers/gpu/drm/i915/display/intel_cmtg_regs.h
> index a4a2a2fe6b66..18dcb665df04 100644
> --- a/drivers/gpu/drm/i915/display/intel_cmtg_regs.h
> +++ b/drivers/gpu/drm/i915/display/intel_cmtg_regs.h
> @@ -32,4 +32,10 @@
> #define CMTG_HW_GB_DC5_EXIT_LATENCY_MASK REG_GENMASK(27, 16)
> #define CMTG_HW_GB_UP_LW_BG_DIFF_MASK
> REG_GENMASK(31, 28)
>
> +#define _CMTG_SCANLINE_GB1_A 0x456A0
> +#define _CMTG_SCANLINE_GB1_B 0x456C0
> +#define CMTG_SCANLINE_GB1(trans) _MMIO_TRANS((trans), \
> + _CMTG_SCANLINE_GB1_A,
> _CMTG_SCANLINE_GB1_B)
> +#define CMTG_HW_GB_ENABLE REG_BIT(31)
> +
> #endif /* __INTEL_CMTG_REGS_H__ */
> --
> 2.29.0
