On Xe3P, DC3CO entry during an active frame can leave the pipe in a bad state and does not recover well.
Set CHICKEN_DCPR_4 bit 24 to inform DMC to block DC3CO entry. v2: - Add HSD number to intel_display_wa framework. Dibin Moolakadan Subrahmanian (1): drm/i915/psr: Block DC3CO entry during active frame .../gpu/drm/i915/display/intel_display_regs.h | 3 +++ drivers/gpu/drm/i915/display/intel_display_wa.c | 2 ++ drivers/gpu/drm/i915/display/intel_display_wa.h | 1 + drivers/gpu/drm/i915/display/intel_psr.c | 16 ++++++++++++++++ 4 files changed, 22 insertions(+) -- 2.43.0
