intel_dp_mode_valid_downstream() uses the intel_dp_hdmi_sink_max_frl() to check if FRL is to be used, in order to skip the max dotclock limit for the FRL cases.
Instead, use the intel_dp_pcon_sink_support_frl() that check both sink and the pcon's FRL capabilities. Signed-off-by: Ankit Nautiyal <[email protected]> --- drivers/gpu/drm/i915/display/intel_dp.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/gpu/drm/i915/display/intel_dp.c b/drivers/gpu/drm/i915/display/intel_dp.c index 6bf42128a81d..d2d330b6c39a 100644 --- a/drivers/gpu/drm/i915/display/intel_dp.c +++ b/drivers/gpu/drm/i915/display/intel_dp.c @@ -1237,7 +1237,7 @@ intel_dp_mode_valid_downstream(struct intel_connector *connector, struct intel_dp *intel_dp = intel_attached_dp(connector); int bpc = 8; /* Assume 8bpc for the DP++/HDMI/DVI TMDS/FRL bw check */ - if (!intel_dp_hdmi_sink_max_frl(intel_dp) && + if (!intel_dp_pcon_sink_support_frl(intel_dp) && intel_dp->dfp.max_dotclock && target_clock > intel_dp->dfp.max_dotclock) return MODE_CLOCK_HIGH; -- 2.50.1
