On Mon, 03 Aug 2026, Michał Grzelak <[email protected]> wrote: > Indent SKL_DSSM register macros. Define mask and register values with > REG_GENMASK() and REG_FIELD_PREP() instead of bit shifts.
Nitpick, in subject, "fix" is misleading. This is just cleanup without functional changes. No need to resend for this. Reviewed-by: Jani Nikula <[email protected]> > > v1->v2 > - s/REG_GENMASK/REG_FIELD_PREP/ (Jani) > > Signed-off-by: Michał Grzelak <[email protected]> > --- > drivers/gpu/drm/i915/display/intel_display_regs.h | 8 ++++---- > 1 file changed, 4 insertions(+), 4 deletions(-) > > diff --git a/drivers/gpu/drm/i915/display/intel_display_regs.h > b/drivers/gpu/drm/i915/display/intel_display_regs.h > index 0f5018482497..740331ead20a 100644 > --- a/drivers/gpu/drm/i915/display/intel_display_regs.h > +++ b/drivers/gpu/drm/i915/display/intel_display_regs.h > @@ -1779,10 +1779,10 @@ > #define XE2LPD_DE_CAP_SCALER_SINGLE 1 > > #define SKL_DSSM _MMIO(0x51004) > -#define ICL_DSSM_CDCLK_PLL_REFCLK_MASK (7 << 29) > -#define ICL_DSSM_CDCLK_PLL_REFCLK_24MHz (0 << 29) > -#define ICL_DSSM_CDCLK_PLL_REFCLK_19_2MHz (1 << 29) > -#define ICL_DSSM_CDCLK_PLL_REFCLK_38_4MHz (2 << 29) > +#define ICL_DSSM_CDCLK_PLL_REFCLK_MASK REG_GENMASK(31, 29) > +#define ICL_DSSM_CDCLK_PLL_REFCLK_24MHz > REG_FIELD_PREP(ICL_DSSM_CDCLK_PLL_REFCLK_MASK, 0) > +#define ICL_DSSM_CDCLK_PLL_REFCLK_19_2MHz > REG_FIELD_PREP(ICL_DSSM_CDCLK_PLL_REFCLK_MASK, 1) > +#define ICL_DSSM_CDCLK_PLL_REFCLK_38_4MHz > REG_FIELD_PREP(ICL_DSSM_CDCLK_PLL_REFCLK_MASK, 2) > > /*GEN11 chicken */ > #define _PIPEA_CHICKEN 0x70038 -- Jani Nikula, Intel
