> Subject: [PATCH v4 02/12] drm/i915/vrr: Use the helper to write > EMP_AS_SDP_TL register > > Now that intel_dip_write_emp_as_sdp_tl() exists, use it instead of the open- > coded EMP_AS_SDP_TL programming sequence in > intel_vrr_set_transcoder_timings(). > > Signed-off-by: Ankit Nautiyal <[email protected]>
LGTM, Reviewed-by: Suraj Kandpal <[email protected]> > --- > drivers/gpu/drm/i915/display/intel_vrr.c | 14 ++------------ > 1 file changed, 2 insertions(+), 12 deletions(-) > > diff --git a/drivers/gpu/drm/i915/display/intel_vrr.c > b/drivers/gpu/drm/i915/display/intel_vrr.c > index 6130854a706c..a3dfeaa12e8b 100644 > --- a/drivers/gpu/drm/i915/display/intel_vrr.c > +++ b/drivers/gpu/drm/i915/display/intel_vrr.c > @@ -9,7 +9,7 @@ > #include "intel_alpm.h" > #include "intel_crtc.h" > #include "intel_de.h" > -#include "intel_dip_regs.h" > +#include "intel_dip.h" > #include "intel_display_regs.h" > #include "intel_display_types.h" > #include "intel_dmc.h" > @@ -658,17 +658,7 @@ void intel_vrr_set_transcoder_timings(const struct > intel_crtc_state *crtc_state) > VRR_VSYNC_END(crtc_state->vrr.vsync_end) | > VRR_VSYNC_START(crtc_state->vrr.vsync_start)); > > - /* > - * For BMG and LNL+ onwards the EMP_AS_SDP_TL is used for > programming > - * double buffering point and transmission line for VRR packets for > - * HDMI2.1/DP/eDP/DP->HDMI2.1 PCON. > - * Since currently we support VRR only for DP/eDP, so this is > programmed > - * to for Adaptive Sync SDP to Vsync start. > - */ > - if (DISPLAY_VERx100(display) == 1401 || DISPLAY_VER(display) >= 20) > - intel_de_write(display, > - EMP_AS_SDP_TL(display, cpu_transcoder), > - EMP_AS_SDP_DB_TL(crtc_state->vrr.vsync_start)); > + intel_dip_write_emp_as_sdp_tl(crtc_state); > } > > void > -- > 2.45.2
