> Subject: [PATCH v4 01/12] drm/i915/dip: Add new file to handle Data Island > Packet hardware > > Add new files intel_dip.c, intel_dip.h, and intel_dip_regs.h to handle low > level > hardware programming related to Data Island Packets. > > Currently only programming of the Transmission Line for HDMI 2.1 Extended > Metadata Packet (EMP) and DP Adaptive-Sync Secondary Data Packet (SDP) is > added (MMIO register EMP_AS_SDP_TL). > > This will serve as a common place for DIP related code, which is currently > scattered across DP and HDMI files. A TODO has been added for extracting the > remaining DIP helpers. > > Signed-off-by: Ankit Nautiyal <[email protected]>
LGTM, Reviewed-by: Suraj Kandpal <[email protected]> > --- > drivers/gpu/drm/i915/Makefile | 1 + > drivers/gpu/drm/i915/display/intel_dip.c | 39 +++++++++++++++++++ > drivers/gpu/drm/i915/display/intel_dip.h | 38 ++++++++++++++++++ > drivers/gpu/drm/i915/display/intel_dip_regs.h | 17 ++++++++ > drivers/gpu/drm/i915/display/intel_vrr.c | 1 + > drivers/gpu/drm/i915/display/intel_vrr_regs.h | 6 --- > drivers/gpu/drm/xe/Makefile | 1 + > 7 files changed, 97 insertions(+), 6 deletions(-) create mode 100644 > drivers/gpu/drm/i915/display/intel_dip.c > create mode 100644 drivers/gpu/drm/i915/display/intel_dip.h > create mode 100644 drivers/gpu/drm/i915/display/intel_dip_regs.h > > diff --git a/drivers/gpu/drm/i915/Makefile b/drivers/gpu/drm/i915/Makefile > index 07802a7f4ce5..04624d35447c 100644 > --- a/drivers/gpu/drm/i915/Makefile > +++ b/drivers/gpu/drm/i915/Makefile > @@ -349,6 +349,7 @@ i915-y += \ > display/intel_cx0_phy.o \ > display/intel_ddi.o \ > display/intel_ddi_buf_trans.o \ > + display/intel_dip.o \ > display/intel_display_device.o \ > display/intel_display_trace.o \ > display/intel_dkl_phy.o \ > diff --git a/drivers/gpu/drm/i915/display/intel_dip.c > b/drivers/gpu/drm/i915/display/intel_dip.c > new file mode 100644 > index 000000000000..2e2bdb2b199c > --- /dev/null > +++ b/drivers/gpu/drm/i915/display/intel_dip.c > @@ -0,0 +1,39 @@ > +// SPDX-License-Identifier: MIT > +/* > + * Copyright © 2026 Intel Corporation > + * > + */ > + > +#include "intel_de.h" > +#include "intel_dip.h" > +#include "intel_dip_regs.h" > +#include "intel_display_types.h" > + > +u16 intel_dip_read_emp_as_sdp_tl(const struct intel_crtc_state > +*crtc_state) { > + struct intel_display *display = to_intel_display(crtc_state); > + enum transcoder cpu_transcoder = crtc_state->cpu_transcoder; > + u32 val; > + > + if (!HAS_EMP_AS_SDP_TL(display)) > + return 0; > + > + val = intel_de_read(display, EMP_AS_SDP_TL(display, cpu_transcoder)); > + return REG_FIELD_GET(EMP_AS_SDP_DB_TL_MASK, val); } > + > +void intel_dip_write_emp_as_sdp_tl(const struct intel_crtc_state > +*crtc_state) { > + struct intel_display *display = to_intel_display(crtc_state); > + enum transcoder cpu_transcoder = crtc_state->cpu_transcoder; > + > + if (!HAS_EMP_AS_SDP_TL(display)) > + return; > + /* > + * Since currently we support VRR only for DP/eDP, so this is > programmed > + * only for Adaptive Sync SDP to Vsync start. > + */ > + intel_de_write(display, > + EMP_AS_SDP_TL(display, cpu_transcoder), > + EMP_AS_SDP_DB_TL(crtc_state->vrr.vsync_start)); > +} > diff --git a/drivers/gpu/drm/i915/display/intel_dip.h > b/drivers/gpu/drm/i915/display/intel_dip.h > new file mode 100644 > index 000000000000..25bae4a04d6b > --- /dev/null > +++ b/drivers/gpu/drm/i915/display/intel_dip.h > @@ -0,0 +1,38 @@ > +/* SPDX-License-Identifier: MIT */ > +/* > + * Copyright © 2026 Intel Corporation > + */ > + > +#ifndef __INTEL_DIP_H__ > +#define __INTEL_DIP_H__ > + > +#include "intel_display_device.h" > + > +/* > + * Video DIP (Data Island Packet) helpers. > + * > + * This file contains helpers for programming video DIP related hardware. > + * > + * TODO: Currently, this is only used for programming EMP_AS_SDP_TL > +i.e. to > + * program Transmission Line for HDMI 2.1 Extended Metadata Packet > +(EMP) and > + * DP Adaptive Sync (AS) Secondary Data Packet (SDP). However, all low > +level > + * DIP buffer read/write and related helpers should be extracted here later. > + */ > + > +struct intel_crtc_state; > + > +/* > + * EMP AS SDP TL: Extended Metadata Packet (EMP) Adaptive Sync (AS) > + * Secondary Data Packet (SDP) Transmission Line (TL). > + * > + * Starting with BMG (display ver 14.01) and LNL+ (display ver 20+), > + * the AS SDP transmission line is programmable via the EMP AS SDP TL > + * register. > + */ > +#define HAS_EMP_AS_SDP_TL(__display) (DISPLAY_VERx100(__display) > == 1401 || \ > + DISPLAY_VER(__display) >= 20) > + > +u16 intel_dip_read_emp_as_sdp_tl(const struct intel_crtc_state > +*crtc_state); void intel_dip_write_emp_as_sdp_tl(const struct > +intel_crtc_state *crtc_state); > + > +#endif /* __INTEL_DIP_H__ */ > diff --git a/drivers/gpu/drm/i915/display/intel_dip_regs.h > b/drivers/gpu/drm/i915/display/intel_dip_regs.h > new file mode 100644 > index 000000000000..85dcbf42e77d > --- /dev/null > +++ b/drivers/gpu/drm/i915/display/intel_dip_regs.h > @@ -0,0 +1,17 @@ > +/* SPDX-License-Identifier: MIT */ > +/* > + * Copyright © 2026 Intel Corporation > + */ > + > +#ifndef __INTEL_DIP_REGS_H__ > +#define __INTEL_DIP_REGS_H__ > + > +#include "intel_display_reg_defs.h" > + > +/* EMP (Extended Metadata Packet) AS (Adaptive Sync) SDP Transmission Line > */ > +#define _EMP_AS_SDP_TL_A 0x60204 > +#define EMP_AS_SDP_TL(display, trans) > _MMIO_TRANS2((display), (trans), _EMP_AS_SDP_TL_A) > +#define EMP_AS_SDP_DB_TL_MASK REG_GENMASK(12, 0) > +#define EMP_AS_SDP_DB_TL(db_transmit_line) > REG_FIELD_PREP(EMP_AS_SDP_DB_TL_MASK, (db_transmit_line)) > + > +#endif /* __INTEL_DIP_REGS_H__ */ > diff --git a/drivers/gpu/drm/i915/display/intel_vrr.c > b/drivers/gpu/drm/i915/display/intel_vrr.c > index e03b5daac5be..6130854a706c 100644 > --- a/drivers/gpu/drm/i915/display/intel_vrr.c > +++ b/drivers/gpu/drm/i915/display/intel_vrr.c > @@ -9,6 +9,7 @@ > #include "intel_alpm.h" > #include "intel_crtc.h" > #include "intel_de.h" > +#include "intel_dip_regs.h" > #include "intel_display_regs.h" > #include "intel_display_types.h" > #include "intel_dmc.h" > diff --git a/drivers/gpu/drm/i915/display/intel_vrr_regs.h > b/drivers/gpu/drm/i915/display/intel_vrr_regs.h > index 9d4d6573a149..ba8631cbc672 100644 > --- a/drivers/gpu/drm/i915/display/intel_vrr_regs.h > +++ b/drivers/gpu/drm/i915/display/intel_vrr_regs.h > @@ -174,12 +174,6 @@ > #define VRR_VSYNC_START_MASK REG_GENMASK(12, 0) > #define VRR_VSYNC_START(vsync_start) > REG_FIELD_PREP(VRR_VSYNC_START_MASK, (vsync_start)) > > -/* Common register for HDMI EMP and DP AS SDP */ > -#define _EMP_AS_SDP_TL_A 0x60204 > -#define EMP_AS_SDP_TL(display, trans) > _MMIO_TRANS2((display), (trans), _EMP_AS_SDP_TL_A) > -#define EMP_AS_SDP_DB_TL_MASK REG_GENMASK(12, 0) > -#define EMP_AS_SDP_DB_TL(db_transmit_line) > REG_FIELD_PREP(EMP_AS_SDP_DB_TL_MASK, (db_transmit_line)) > - > #define _TRANS_CMRR_M_LO_A 0x604F0 > #define TRANS_CMRR_M_LO(display, trans) > _MMIO_TRANS2((display), (trans), _TRANS_CMRR_M_LO_A) > > diff --git a/drivers/gpu/drm/xe/Makefile b/drivers/gpu/drm/xe/Makefile index > 09661f079d03..9e826d164951 100644 > --- a/drivers/gpu/drm/xe/Makefile > +++ b/drivers/gpu/drm/xe/Makefile > @@ -256,6 +256,7 @@ xe-$(CONFIG_DRM_XE_DISPLAY) += \ > i915-display/intel_ddi.o \ > i915-display/intel_ddi_buf_trans.o \ > i915-display/intel_de.o \ > + i915-display/intel_dip.o \ > i915-display/intel_display.o \ > i915-display/intel_display_conversion.o \ > i915-display/intel_display_device.o \ > -- > 2.45.2
