> Subject: [PATCH v4 04/12] drm/i915/dp: Add helper to get AS SDP Transmission > Line > > Introduce a DP helper to compute the Adaptive Sync SDP transmission line and > use it when programming the EMP_AS_SDP_TL register. > > Currently the AS SDP transmission line is programmed to the T1 position. > This can be extended in the future to support programming the T2 position as > well. > > While at it, improve the documentation: the AS SDP transmission line > corresponds to the T1 position, which maps to the start of the VSYNC pulse. > > Signed-off-by: Ankit Nautiyal <[email protected]>
LGTM, Reviewed-by: Suraj Kandpal <[email protected]> > --- > drivers/gpu/drm/i915/display/intel_dip.c | 7 ++++--- > drivers/gpu/drm/i915/display/intel_dp.c | 12 ++++++++++++ > drivers/gpu/drm/i915/display/intel_dp.h | 1 + > 3 files changed, 17 insertions(+), 3 deletions(-) > > diff --git a/drivers/gpu/drm/i915/display/intel_dip.c > b/drivers/gpu/drm/i915/display/intel_dip.c > index 450a599b5053..504a2edadd0e 100644 > --- a/drivers/gpu/drm/i915/display/intel_dip.c > +++ b/drivers/gpu/drm/i915/display/intel_dip.c > @@ -8,6 +8,7 @@ > #include "intel_dip.h" > #include "intel_dip_regs.h" > #include "intel_display_types.h" > +#include "intel_dp.h" > > u16 intel_dip_read_emp_as_sdp_tl(const struct intel_crtc_state *crtc_state) > { > @@ -32,11 +33,11 @@ void intel_dip_write_emp_as_sdp_tl(const struct > intel_crtc_state *crtc_state) > return; > /* > * Since currently we support VRR only for DP/eDP, program the register > - * for Adaptive Sync SDP using vsync start. For non-DP encoders, > - * the register is reset to 0. > + * for Adaptive Sync SDP. For non-DP encoders, the register is reset > + * to 0. > */ > if (intel_crtc_has_dp_encoder(crtc_state)) > - transmission_line = crtc_state->vrr.vsync_start; > + transmission_line = > +intel_dp_get_as_sdp_transmission_line(crtc_state); > > intel_de_write(display, > EMP_AS_SDP_TL(display, cpu_transcoder), diff --git > a/drivers/gpu/drm/i915/display/intel_dp.c > b/drivers/gpu/drm/i915/display/intel_dp.c > index 3569e61e7fee..f54f7faf878f 100644 > --- a/drivers/gpu/drm/i915/display/intel_dp.c > +++ b/drivers/gpu/drm/i915/display/intel_dp.c > @@ -7465,3 +7465,15 @@ void intel_dp_link_cleanup(struct intel_dp > *intel_dp) { > intel_dp_link_training_cleanup(intel_dp->link.training); > } > + > +int intel_dp_get_as_sdp_transmission_line(const struct intel_crtc_state > +*crtc_state) { > + /* > + * EMP_AS_SDP_TL defines the T1 position as the default AS SDP > + * Transmission Line, which corresponds to the start of the > + * VSYNC pulse. > + * > + * Use the T1 position for now. > + */ > + return crtc_state->vrr.vsync_start; > +} > diff --git a/drivers/gpu/drm/i915/display/intel_dp.h > b/drivers/gpu/drm/i915/display/intel_dp.h > index 92ce04852326..fc80b5b64785 100644 > --- a/drivers/gpu/drm/i915/display/intel_dp.h > +++ b/drivers/gpu/drm/i915/display/intel_dp.h > @@ -238,6 +238,7 @@ bool intel_dp_joiner_candidate_valid(struct > intel_connector *connector, > for_each_if(intel_dp_joiner_candidate_valid(__connector, > (__mode)->hdisplay, __num_joined_pipes)) > > u8 intel_dp_as_sdp_transmission_time(void); > +int intel_dp_get_as_sdp_transmission_line(const struct intel_crtc_state > +*crtc_state); > > int intel_dp_link_init(struct intel_dp *intel_dp); void > intel_dp_link_cleanup(struct intel_dp *intel_dp); > -- > 2.45.2
