> Subject: [PATCH v4 08/12] drm/i915/display: Add HAS_COMMON_SDP_TL > macro >
Maybe drm/i915/dip Otherwise LGTM, Reviewed-by: Suraj Kandpal <[email protected]> > Add a helper macro to detect CMN SDP TL support on platforms with display > version 35 and above. > > Signed-off-by: Ankit Nautiyal <[email protected]> > --- > drivers/gpu/drm/i915/display/intel_dip.h | 10 ++++++++++ > 1 file changed, 10 insertions(+) > > diff --git a/drivers/gpu/drm/i915/display/intel_dip.h > b/drivers/gpu/drm/i915/display/intel_dip.h > index 600dabbf7372..e9959356226e 100644 > --- a/drivers/gpu/drm/i915/display/intel_dip.h > +++ b/drivers/gpu/drm/i915/display/intel_dip.h > @@ -32,6 +32,16 @@ struct intel_crtc_state; > #define HAS_EMP_AS_SDP_TL(__display) (DISPLAY_VERx100(__display) > == 1401 || \ > DISPLAY_VER(__display) >= 20) > > +/* > + * CMN SDP TL: Common Secondary Data Packet Transmission Line. > + * > + * Xe3p_lpd introduces new register CMN_SDP_TL to program a common SDP > + * Transmission line that will be used by the Hardware to position the > + * SDPs. Along with this, another new register CMN_SDP_TL_STGR_CTL is > + * also added to stagger the different SDPs. > + */ > +#define HAS_COMMON_SDP_TL(__display) (DISPLAY_VER(__display) >= 35) > + > u16 intel_dip_read_emp_as_sdp_tl(const struct intel_crtc_state *crtc_state); > void intel_dip_write_emp_as_sdp_tl(const struct intel_crtc_state *crtc_state); > > -- > 2.45.2
