From: Ankit Nautiyal <[email protected]> On BMG platforms, the standard M/N ratio limit of 10 can be bypassed under specific conditions, as permitted by hardware capabilities.
Modify the helper intel_dp_can_support_m_n() to account for this by checking whether the platform supports bypassing the limit. The workaround is only intended for 128b/132b links, so restrict it to those. During the mode_valid phase, the check assumes that PIPE_A will be used, to allow the mode where the M/N ratio is within the limits for the workaround. v2: -Keep the helper static: the MST mode_valid now goes through the shared intel_dp_mode_valid_m_n() rather than calling it directly, so it no longer needs to be exported. Signed-off-by: Ankit Nautiyal <[email protected]> Signed-off-by: Suraj Kandpal <[email protected]> --- drivers/gpu/drm/i915/display/intel_dp.c | 18 +++++++++++++++--- 1 file changed, 15 insertions(+), 3 deletions(-) diff --git a/drivers/gpu/drm/i915/display/intel_dp.c b/drivers/gpu/drm/i915/display/intel_dp.c index 9c327008b733..9af525e9b58d 100644 --- a/drivers/gpu/drm/i915/display/intel_dp.c +++ b/drivers/gpu/drm/i915/display/intel_dp.c @@ -1277,9 +1277,11 @@ intel_dp_get_max_m_n_ratio(struct intel_display *display) static bool intel_dp_can_support_m_n(struct intel_display *display, + const struct intel_crtc_state *crtc_state, int pixel_clock, int link_rate) { int max_m_n_ratio = intel_dp_get_max_m_n_ratio(display); + enum pipe pipe = PIPE_A; u32 link_m, link_n; int m_n_ratio; @@ -1291,7 +1293,16 @@ intel_dp_can_support_m_n(struct intel_display *display, m_n_ratio = DIV_ROUND_UP(link_m, link_n); - return m_n_ratio <= max_m_n_ratio; + if (m_n_ratio <= max_m_n_ratio) + return true; + + if (!drm_dp_is_uhbr_rate(link_rate)) + return false; + + if (crtc_state) + pipe = to_intel_crtc(crtc_state->uapi.crtc)->pipe; + + return intel_display_can_bypass_m_n_limit(display, m_n_ratio, pipe); } static int intel_dp_mso_pixel_clock(struct intel_dp *intel_dp, int pixel_clock) @@ -1352,7 +1363,7 @@ bool intel_dp_mode_valid_m_n(struct intel_dp *intel_dp, int pixel_clock) intel_dp_link_caps_iter_start(&iter, intel_dp->link.caps, order, INTEL_DP_LINK_CAPS_FILTER_ALL); for_each_dp_link_config(&iter, &link_config) { - if (intel_dp_can_support_m_n(display, m_n_pixel_clock, + if (intel_dp_can_support_m_n(display, NULL, m_n_pixel_clock, link_config.rate)) { found = true; @@ -2741,7 +2752,8 @@ intel_dp_compute_m_n_ratio_limits(struct intel_dp *intel_dp, intel_dp_link_caps_iter_start(&iter, link_caps, order, limits->link_config_filter); for_each_dp_link_config(&iter, &link_config) { - if (!intel_dp_can_support_m_n(display, pixel_clock, link_config.rate)) + if (!intel_dp_can_support_m_n(display, crtc_state, pixel_clock, + link_config.rate)) continue; intel_dp_link_caps_filter_add(link_caps, &new_filter, &link_config); -- 2.34.1
